OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 9.3.200.277 SF-TIB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.; $Circuit$IAM'@;XXT_0FAF10A020251210163517CxxT_0FAF0CE020251210163517C  T_0FAF092020251210163517?T_0FAF056020251210163517?`x@`x`@T_0FAF01A020251210163517?hhhT_0FAEFDE020251210163517?@h`@h`h`T_0FAEE76020251210163517;0X0XT_0FAEF2A020251210163517?00T_0F349AB020251210163517?T_0F349E7020251210163517?XXXT_0F34A23020251210163517?T_0F34A5F020251210163517?T_0F34A9B020251210163517;0P0PT_0F34AD7020251210163517?0X00XX0T_0F34B13020251210163517?0P0PPT_0F34B4F020251210163517?PPPPPT_0F34B8B020251210163517;PPPPT_0F34BC7020251210163517;xxT_0F34C03020251210163517;xxT_0F34C3F020251210163517;T_0F34C7B020251210163517;xxT_0F34CB7020251210163517;((T_0F9E25E020251210163517?hhhT_0F9E29A020251210163517?h0h0h0T_0F9E2D6020251210163517?T_0F9E312020251210163517?xhxxhhxT_0F9E34E020251210163517?  T_0F9E38A020251210163517?x0xx00xT_0F9E3C6020251210163517;T_0F9E402020251210163517;HHHHT_0F9E43E020251210163517;XhXhT_0F9E47A020251210163517;XhXhT_0F9E4B6020251210163517;00T_0F9E4F2020251210163517;00T_0F9E52E020251210163517;T_0F9E56A020251210163517;88T_0F9E5A6020251210163517;T_0F9E5E2020251210163517?T_0F9E61E020251210163517?  T_0F9E65A020251210163517?(0(00T_0F9E696020251210163517?0 80 0 8T_0F9E6D2020251210163517:B(PU1T_0E68A8A020251210162841 PGA848PGA848RC:\Users\a0232807\AppData\Local\Temp\DesignSoft\{Tina9-TI-07092020-090452}\PGA848SCK#PGA848Label[QPPPPd.INP 0 @d.INNIN- x @d.VS-S 8 @d.VS+ 8 @d.LVDDN+  @d.DGND X @d.A0F  @d.REF @ @d.A1ND  @d.DA_IN+ X( @d.A2+  @d.LVSS  @d.DA_IN- X @d.OUT XX @ffP 5v@ 5v@( * PGA848y************************************************************************************************************************O* (C) Copyright 2025 Texas Instruments Incorporated. All rights reserved. y************************************************************************************************************************N** This model is designed as an aid for customers of Texas Instruments. N** TI and its licensors and suppliers make no warranties, either expressed N** or implied, with respect to this model, including the warranties of M** merchantability or fitness for a particular purpose. The model is M** provided solely on an "as is" basis. The entire risk as to its quality (** and performance is with the customery************************************************************************************************************************$* Released by: Gerasimos Madalvanos* Date: 12/10/2025* Part: PGA848*8* Model Type: Generic (suitable for all analysis types)&* Created by: Srivatsan Sathyamoorthy?* Model Architecture: TI PRAMPS Properitary Model Architecture** Top Level Model: PGA848* Model Version: 1.0*y************************************************************************************************************************T* MACRO-MODEL SIMULATED PARAMETERS: Across all GAIN CONFIGURATIONS unless specified7******************************************************* AC PARAMETERS**********************>* CLOSED-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zout vs. Freq.)P* CLOSED-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Acl vs. Freq.)B* COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR vs. Freq.) G=16C* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR vs. Freq.) G=16;* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en vs. Freq.);* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in vs. Freq.)O* OUTPUT COMMON-MODE VOLTAGE BANDWIDTH, OUTPUT BALANCE, INPUT IMPEDANCE (Vocm)*********************** DC PARAMETERS**********************(* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)2* INPUT BIAS CURRENT and OFFSET CURRENT (Ib, Ios)6* INPUT OFFSET VOLTAGE VS. TEMPERATURE (Vos vs. Temp)K* OUTPUT COMMON-MODE VOLTAGE OFFSET VOLTAGE VS. TEMPERATURE (Vos vs. Temp):* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vout vs. Iout)%* SHORT-CIRCUIT OUTPUT CURRENT (Isc),* QUIESCENT CURRENT (Iq* *-For all pinouts)*********************** TRANSIENT PARAMETERS*********************** SLEW RATE (SR))* SETTLING TIME VS. CAPACITIVE LOAD (ts)****  E.SUBCKT PGA848 A0 A1 A2 DA_IN+ DA_IN- DGND INN INP LVDD LVSS OUT REF + VS+ VS- D_D19 LVDD VS+ DIO_ESD D_D9 VS- INN DIO_ESD D_D8 VS- INP DIO_ESD D_D28 LVSS REF DIO_ESD /R_R4 FE_OUTP N3270052 3.3333k TC=0,0 ;X_PGA849_BE_X1 DA_IN+ DA_IN- LVDD LVSS OUT VS+ VS- BE_v1 D_D1 INP VS+ DIO_ESD D_D15 A2 VS+ DIO_ESD D_D22 VS- A1 DIO_ESD *R_R1 DA_IN- OUT 6.66591k TC=0,0 CX_PGA85x_FE1 A0 A1 A2 DGND INP INN FE_OUTP FE_OUTN VS+ VS- FE_v1 D_D18 DGND VS+ DIO_ESD "I_I1 0 REF DC 142.6uAdc D_D20 LVSS VS+ DIO_ESD +R_R6 REF N3270052 6.6667k TC=0,0 D_D26 VS- LVSS DIO_ESD D_D16 A1 VS+ DIO_ESD -R_R3 FE_OUTN DA_IN- 3.3333k TC=0,0 D_D24 VS- DGND DIO_ESD D_D27 REF LVDD DIO_ESD D_D23 VS- A0 DIO_ESD D_D21 VS- A2 DIO_ESD D_D25 VS- LVDD DIO_ESD D_D2 INN VS+ DIO_ESD BX_U1 N3270052 DA_IN+ VNSE1 PARAMS: FLW=50 NLF=1 NVR=5.75'C_C1 DA_IN- OUT {CF} TC=0,0 D_D17 A0 VS+ DIO_ESD .PARAM cf=1f.ENDS D.SUBCKT FE_v1 ALT0GT ALT1GT ALT2GT DGND IN+ IN- OUT+ OUT- VS+ VS- MX_VGA_sch1 ALT0GT ALT1GT ALT2GT N3267786 OUTN_G0P125 OUTP_G0P125 OUTN_G0P250K+ OUTP_G0P250 OUTN_G0P500 OUTP_G0P500 OUTN_G01 OUTP_G01 OUTN_G02 OUTP_G02L+ OUTN_G04 OUTP_G04 OUTN_G08 OUTP_G08 OUTN_G16 OUTP_G16 OUT+ OUT- N3264246*+ N3264286 VariableGainAmplifier_Ideal JX_PGA85x_GS_v1 ALT0GT ALT1GT ALT2GT DGND N3267786 OUTN_G0P125 OUTP_G0P125N+ OUTN_G0P250 OUTP_G0P250 OUTN_G0P500 OUTP_G0P500 OUTN_G01 OUTP_G01 OUTN_G02R+ OUTP_G02 OUTN_G04 OUTP_G04 OUTN_G08 OUTP_G08 OUTN_G16 OUTP_G16 IN+ IN- VS+ VS-$+ N3264286 N3264246 GainStage_v1 .ENDS N.SUBCKT GainStage_v1 ALT0GT ALT1GT ALT2GT DGND DGND_B G0p500N G0p500P G1N G1PR+ G2N G2P G5N G5P G10N G10P G20N G20P G50N G50P G100N G100P IN+ IN- V+ V- Vn Vp + #C_C6 MID ESDP 7p TC=0,0 %G_G_VSN_BUFFER1 VN 0 V- 0 -1+R_RCM1 MID N2164268 R_NOISELESS 1T$R_R_MID7 VN 0 R_NOISELESS 16R_R51 G20N G50N 4.62428571428571E+03 TC=0,0 +R_RCM9 MID N3588855 R_NOISELESS 1T)C_C2 G100P N00330 4.2p TC=0,0 %I_IQ_INPUT1 V+ V- DC 3mAdc 0X_S1 LINE7 DGND G100N V2I_N GainStage_v1_S1 #I_I5 MID ESDP DC 500pAdc $I_I1 VP N00363 DC 500uAdc #I_I6 ESDN MID DC 500pAdc %V_VCM_MAX1 N2164268 VP -3Vdc'C_Ccm3 MID DGND_B 1f TC=0,0 $C_Ccm1 MID INN 1f TC=0,0 ;R_R10 RG_REF G0P500N 7.44434523809524E+01 TC=0,0 $E_E_MID1 MID 0 N2161216 0 14R_R_MID3 N2161216 N2161400 R_NOISELESS 1MEGOX_U6 DGND MID N3588945 MID N3588855 N3589047 VCM_CLAMP PARAMS: GAIN=1)C_C1 G100N N00363 4.2p TC=0,0 /X_S8 LINE4 DGND G10P V2I_P GainStage_v1_S8 /X_S3 LINE6 DGND G50N V2I_N GainStage_v1_S3 0X_S10 LINE3 DGND G5P V2I_P GainStage_v1_S10 4R_R55 G1N G2N 1.48800595238095E+02 TC=0,0 !R_R28 ESDN MID RIDEAL 1G"R_R27 ESDN ESDP RIDEAL 1GOX_U2 IN_P MID N2165175 MID N2165087 N2165275 VCM_CLAMP PARAMS: GAIN=1$V_VCM_MIN2 N2165275 VN 3Vdc'G_G_VSP_BUFFER2 VPG 0 VP 0 -20/X_S7 LINE4 DGND G10N V2I_N GainStage_v1_S7 /X_S6 LINE5 DGND G20P V2I_P GainStage_v1_S6 *R_RCM5 N2164356 MID R_NOISELESS 1"R_R29 IN- ESDN RIDEAL 10m+R_R_MID6 N2161216 0 R_NOISELESS 1T6R_R52 G10N G20N 1.50080952380952E+03 TC=0,0 %V_VCM_MAX3 N3588855 VP -4Vdc(G_G_GSn2 N00330 G2P INP G2P 19m*R_RCM6 N2165175 MID R_NOISELESS 1'I_IQ_DGND1 DGND MID DC 4uAdc (I_IQ_A1 ALT2GT MID DC 1.5uAdc /X_S4 LINE6 DGND G50P V2I_P GainStage_v1_S4 /R_RCM10 N3588945 DGND_B R_NOISELESS 1m"R_R25 IN+ ESDP RIDEAL 10m1X_U4 ESDP N3551807 VNSE2 PARAMS: NVR=5.4+R_RCM4 N2165175 INP R_NOISELESS 1m,R_R_MID4 N2161400 VN R_NOISELESS 1m0X_S2 LINE7 DGND G100P V2I_P GainStage_v1_S2 OX_U1 IN_N MID N2164356 MID N2164268 N2164456 VCM_CLAMP PARAMS: GAIN=1$I_I2 VP N00330 DC 500uAdc +R_RCM8 N2165275 MID R_NOISELESS 1T$V_VCM_MIN1 N2164456 VN 3Vdc,R_R_MID1 VP N2161360 R_NOISELESS 1m'C_C4 0 N2161216 100n TC=0,0 /X_S5 LINE5 DGND G20N V2I_N GainStage_v1_S5 (I_IQ_A2 ALT1GT MID DC 1.5uAdc +R_RCM3 N2164356 INN R_NOISELESS 1mPX_3bitsDecoder1 ALT0GT ALT1GT ALT2GT DGND_B LINE0 LINE1 LINE2 LINE3 LINE4 LINE5%+ LINE6 LINE7 VP VN Decoder_3bits $R_R_MID5 VP 0 R_NOISELESS 1(X_U8 G100N G100P VPG VNG ESD_IN7R_R9 G0P500N G1N 7.44047619047619E+01 TC=0,0 $V_VCM_MIN3 N3589047 VN 0Vdc0X_S14 LINE2 DGND G2P V2I_P GainStage_v1_S14 +R_RCM7 N2164456 MID R_NOISELESS 1T5R_R53 G5N G10N 7.45788690476190E+02 TC=0,0 ;X_A1_AolZo_v1 N00110 N00363 MID G100N VPG VNG A1_AolZo_1 %R_R_MID9 VNG 0 R_NOISELESS 10X_S16 LINE2 DGND G2N V2I_N GainStage_v1_S16 %R_R_MID8 VPG 0 R_NOISELESS 1!R_R26 MID ESDP RIDEAL 1G7R_R50 G50N G100N 8.19940476190476E+03 TC=0,0 #R_R30 ESDN IN_N RIDEAL 10m%V_VCM_MAX2 N2165087 VP -3Vdc+R_RCM2 MID N2165087 R_NOISELESS 1T+R_RCM11 N3588945 MID R_NOISELESS 1%C_C3 0 N2161360 1f TC=0,0 'G_G_VSN_BUFFER2 VNG 0 VN 0 -204R_R_MID2 N2161360 N2161216 R_NOISELESS 1MEG.X_S9 LINE3 DGND G5N V2I_N GainStage_v1_S9 D_D1 V- V+ DIO_ESD !I_I4 G2P VN DC 500uAdc CX_U3 ESDP MID FEMT2 PARAMS: FLWF=0.1 NLFF=1.5e3 NVRF=202.5CX_U7 ESDN MID FEMT2 PARAMS: FLWF=0.1 NLFF=1.5e3 NVRF=202.5V_V1 VP N00110 1Vdc4R_R54 G2N G5N 4.46664821428571E+02 TC=0,0 ;X_A1_AolZo_v2 N00110 N00330 MID G100P VPG VNG A1_AolZo_1 $C_C7 ESDN ESDP 1p TC=0,0 %C_C5 0 N2161400 1f TC=0,0 (G_G_GSn1 N00363 G2N INN G2N 19m#C_C8 ESDN MID 7p TC=0,0 !I_I3 G2N VN DC 500uAdc $C_Ccm2 MID INP 1f TC=0,0 (I_IQ_A3 ALT0GT MID DC 1.5uAdc %G_G_VSP_BUFFER1 VP 0 V+ 0 -1,R_RCM12 N3589047 MID R_NOISELESS 1T%R_R45 MID N3815944 R_IDEAL 1V_V3 N3816464 0 1Vdc4R_R67 G1P G2P 1.48800595238095E+02 TC=0,0 1C_C22 N3815944 N3815926 795.8f TC=0,0 /R_R43 N3815898 N3815908 R_IDEAL 100MEG1C_C21 N3815898 N3815908 795.8f TC=0,0 (G_G4 N3815944 MID VN MID -62.8m&R_R46 MID N3815908 R_IDEAL 406R_R64 G10P G20P 1.50080952380952E+03 TC=0,0 +R_R70 N3625367 N3625359 R_IDEAL 1k8R_R68 G0P500P G1P 7.44047619047619E+01 TC=0,0 1X_S13 LINE0 DGND N3816476 0 GainStage_v1_S13 =X_H1 N3816460 N3816464 N3551807 N3688039 GainStage_v1_H1 =X_H2 N3816468 N3816472 N3688039 N3689734 GainStage_v1_H2 =X_H3 N3816476 N3816480 N3689734 N3625359 GainStage_v1_H3 1X_S11 LINE2 DGND N3816460 0 GainStage_v1_S11 5R_R65 G5P G10P 7.45788690476190E+02 TC=0,0 NX_U5 IN_P N3625367 VOS_DRIFT PARAMS: DC=50.75E-6 POL=1 DRIFT=0.3E-06/R_R44 N3815944 N3815926 R_IDEAL 100MEG&R_R47 MID N3815926 R_IDEAL 407R_R62 G50P G100P 8.19940476190476E+03 TC=0,0 ;R_R69 RG_REF G0P500P 7.44434523809524E+01 TC=0,0 (G_G3 N3815898 MID VP MID -62.8m%R_R42 MID N3815898 R_IDEAL 14R_R66 G2P G5P 4.46664821428571E+02 TC=0,0 V_V5 N3816480 0 1Vdc6R_R63 G20P G50P 4.62428571428571E+03 TC=0,0 5G_G2 N3625367 N3625359 N3815926 N3815908 -1mV_V4 N3816472 0 1Vdc1X_S12 LINE1 DGND N3816468 0 GainStage_v1_S12 .ENDS .MODEL RIDEAL RES(T_ABS=-273)***A.MODEL DIO_ESD D (RS=2 IS=1E-17 TT=1P BV=40 CJO=5E-13 AF=0 KF=0)*** .MODEL R_IDEAL RES (T_ABS=-273)+.SUBCKT A1_AolZo_1 IN+ IN- MID OUT V+ V- $V_VCM_MAX1 N2158815 V+ 0Vdc+R_RCM4 N2159003 MID R_NOISELESS 1TMX_U5 FOLD V+ MID FOLD AOL_GM1_V1 PARAMS: GAIN=-100m IPOS=0 INEG=-1m%C_Ccm1 MID IN_P 1f TC=0,0 $C_C3 MID OUT 500f TC=0,0 LX_U6 FOLD V- MID FOLD AOL_GM1_V1 PARAMS: GAIN=-100m IPOS=1m INEG=0R_R4 MID OUT RIDEAL 5k!R_R6 IN- IN_N RIDEAL 10m(R_RCM3 N15263 MID R_NOISELESS 1HX_U2 IN_CM N00459 VOS_DRIFT PARAMS: DC=10E-6 POL=1 DRIFT=2E-08"I_I1 IN_CM MID DC 5pAdc OX_U1 N00459 MID N15263 MID N2158815 N2159003 VCM_CLAMP PARAMS: GAIN=1HX_U4 FOLD MID MID OUT AOL_GM1_V1 PARAMS: GAIN=-16.15m IPOS=50m + INEG=-50m$V_VCM_MIN1 N2159003 V- 0Vdc#C_C5 IN_N MID 1p TC=0,0 %C_C4 IN_N IN_CM 1p TC=0,0 $C_C2 MID IN_CM 1p TC=0,0 %C_C1 OUT FOLD 6.2p TC=0,0 LX_U7 OUT V+ MID OUT AOL_GM1_V1 PARAMS: GAIN=-100m IPOS=0 INEG=-25m+R_RCM1 MID N2158815 R_NOISELESS 1T!I_I2 IN_N MID DC 5pAdc #R_R3 MID FOLD RIDEAL 50MEG!R_R5 IN_N MID RIDEAL 10TIX_U3 IN_P IN_N MID FOLD AOL_GM1_V1 PARAMS: GAIN=-742u IPOS=100m+ INEG=-100mKX_U8 OUT V- MID OUT AOL_GM1_V1 PARAMS: GAIN=-100m IPOS=25m INEG=0*R_RCM2 N15263 IN_P R_NOISELESS 1m"R_R2 MID IN_CM RIDEAL 10T"R_R1 IN+ IN_CM RIDEAL 10m.ENDS N.SUBCKT Decoder_3bits A0 A1 A2 DGND Line0 Line1 Line2 Line3 Line4 Line5 Line6+ Line7 VS+ VS- @X_NAND2_idealMOS2 N09123 N09123 BBAR DVDD DGND NAND2_idealMOS "R_R3 A0 N09181 RIDEAL 10m7X_NOR3_ideal1 A2 A1 A0 LINE0 DVDD DGND NOR3_idealMOS 9X_NOR3_ideal2 ABAR A1 A0 LINE4 DVDD DGND NOR3_idealMOS &V_VSUBREG_VSN1 DVDD DGND 5Vdc;X_NOR3_ideal6 ABAR BBAR A0 LINE6 DVDD DGND NOR3_idealMOS @X_NAND2_idealMOS1 N09065 N09065 ABAR DVDD DGND NAND2_idealMOS 9X_NOR3_ideal5 A2 BBAR A0 LINE2 DVDD DGND NOR3_idealMOS @X_NAND2_idealMOS3 N09181 N09181 CBAR DVDD DGND NAND2_idealMOS "R_R2 A1 N09123 RIDEAL 10m"R_R1 A2 N09065 RIDEAL 10m;X_NOR3_ideal7 A2 BBAR CBAR LINE3 DVDD DGND NOR3_idealMOS ;X_NOR3_ideal4 ABAR A1 CBAR LINE5 DVDD DGND NOR3_idealMOS 9X_NOR3_ideal3 A2 A1 CBAR LINE1 DVDD DGND NOR3_idealMOS =X_NOR3_ideal8 ABAR BBAR CBAR LINE7 DVDD DGND NOR3_idealMOS .ENDS *.SUBCKT NOR3_idealMOS A B C OUT VDD VSS #R_R3 OUT N02064 RIDEAL 10m0M_M6 OUT C N02181 N02181 MND 0M_M4 OUT A N02181 N02181 MND 3M_M2 N01993 B N00287 N00287 MPD 0M_M5 OUT B N02181 N02181 MND 3M_M3 N02064 C N02072 N02072 MPD #R_R4 VSS N02181 RIDEAL 10m&R_R2 N02072 N01993 RIDEAL 10m-M_M1 N01964 A VDD VDD MPD &R_R1 N00287 N01964 RIDEAL 10m.ENDS ).SUBCKT NAND2_idealMOS A B OUT VDD VSS &R_R3 N01594 N00317 RIDEAL 10m-M_M2 N00299 B VDD VDD MPD #R_R4 VSS N00327 RIDEAL 10m-M_M1 N00293 A VDD VDD MPD #R_R2 OUT N00299 RIDEAL 10m0M_M3 OUT A N00317 N00317 MND 3M_M4 N01594 B N00327 N00327 MND #R_R1 N00293 OUT RIDEAL 10m.ENDS N.SUBCKT VariableGainAmplifier_Ideal ALT0GT ALT1GT ALT2GT DGND G0p125N G0p125PP+ G0p250N G0p250P G0p500N G0p500P G01N G01P G02N G02P G04N G04P G08N G08P G16N+ G16P OUT+ OUT- VS+ VS- 7X_BUF_SWITCH14 DGND LINE6 G08N VOUTN Buffered_Switch E_E1 OUT+ 0 VOUTP 0 19X_BUF_SWITCH3 DGND LINE1 G0P250P VOUTP Buffered_Switch 6X_BUF_SWITCH8 DGND LINE7 G16P VOUTP Buffered_Switch 9X_BUF_SWITCH9 DGND LINE0 G0P125N VOUTN Buffered_Switch 6X_BUF_SWITCH6 DGND LINE6 G08P VOUTP Buffered_Switch 7X_BUF_SWITCH10 DGND LINE4 G02N VOUTN Buffered_Switch NX_3bitsDecoder1 ALT0GT ALT1GT ALT2GT DGND LINE0 LINE1 LINE2 LINE3 LINE4 LINE5'+ LINE6 LINE7 VS+ VS- Decoder_3bits 6X_BUF_SWITCH2 DGND LINE4 G02P VOUTP Buffered_Switch 7X_BUF_SWITCH12 DGND LINE5 G04N VOUTN Buffered_Switch 7X_BUF_SWITCH15 DGND LINE3 G01N VOUTN Buffered_Switch 6X_BUF_SWITCH7 DGND LINE3 G01P VOUTP Buffered_Switch 7X_BUF_SWITCH16 DGND LINE7 G16N VOUTN Buffered_Switch E_E2 OUT- 0 VOUTN 0 16X_BUF_SWITCH4 DGND LINE5 G04P VOUTP Buffered_Switch :X_BUF_SWITCH11 DGND LINE1 G0P250N VOUTN Buffered_Switch 9X_BUF_SWITCH1 DGND LINE0 G0P125P VOUTP Buffered_Switch :X_BUF_SWITCH13 DGND LINE2 G0P500N VOUTN Buffered_Switch 9X_BUF_SWITCH5 DGND LINE2 G0P500P VOUTP Buffered_Switch .ENDS /.SUBCKT Buffered_Switch DGND VEN VSW_I VSW_O 1X_S1 VEN DGND VSW_O VSW_I Buffered_Switch_S1 "C_C1 0 VSW_O 1p TC=0,0 .ENDS ..SUBCKT BE_v1 IN+ IN- LVDD LVSS OUT VS+ VS- !V_V4 N3739216 VS- 1.5Vdc,C_C7 N3977925 VO1P3 {CM1} TC=0,0 MX_U33 VIMON+ V_OUT MID_LV VO1P2 MID MID_LV VO1P3 AOL_GM2_V2 PARAMS: ++ GM2_NO_IOUT=-46m K=1 IPOS=45m INEG=-45m$E_E10 N4053379 0 VIMON 0 1k#C_C23 IN- IN+ 1p TC=0,0 +I_IQ_INPUT2 LVDD LVSS DC 1.3mAdc *R_R37 N3739216 0 R_NOISELESS 100G"R_R6 MIDO VS- 1G TC=0,0 ,R_R2 MID VO1P2 R_NOISELESS 10.95MEG$C_C2 MID VO1P2 1p TC=0,0 MX_U8 VO1P3 LVDD 0 VO1P1 AOL_GM1_V1 PARAMS: GAIN=5.5m IPOS=1m INEG=0E_E2 MID 0 MIDO 0 1.R_R9 VO1P3 N02244 R_NOISELESS {RNULL}0R_R_MID4 N4052120 VSS_LV R_NOISELESS 1m&R_R24 IN- MID R_NOISELESS 10G)C_C3 MID_LV VO1P3 500f TC=0,0 LX_U9 VO1P1 VS+ 0 VO1P1 AOL_GM1_V1 PARAMS: GAIN=-5m IPOS=0 INEG=-1mKX_U4 N3739150 IN- MID VO1P1 AOL_GM1_V1 PARAMS: GAIN=-3m IPOS=662u+ INEG=-662uKX_U12 VS- VO1P1 0 VO1P1 AOL_GM1_V1 PARAMS: GAIN=5m IPOS=1m INEG=0'E_E_MID1 MID_LV 0 N4051938 0 1%C_C5 0 N4052120 1f TC=0,0 (R_R_MID7 VSS_LV 0 R_NOISELESS 1.R_R4 N04481 N3638014 R_NOISELESS 100m'C_C4 0 N4051938 100n TC=0,0 0R_R_MID1 VDD_LV N4052080 R_NOISELESS 1m*X_H1 VO1P3 N3638014 VIMON+ 0 BE_v1_H1 +R_R3 MID_LV VO1P3 R_NOISELESS 126k+G_G_VSN_BUFFER1 VSS_LV 0 LVSS 0 -1"R_R5 VS+ MIDO 1G TC=0,0 *R_R34 0 N3739056 R_NOISELESS 100G D_D1 LVSS LVDD DIO_ESD $X_U31 OUT LVDD LVSS ESD_OUT&R_R23 MID IN+ R_NOISELESS 10G#E_E9 N3715438 0 VIMON 0 1k:X_U28 N4053379 0 LVSS 0 IQ_SRC PARAMS: GAIN=1E-3%C_C1 MID VO1P1 50f TC=0,0 !V_V3 VS+ N3739056 1.5Vdc)R_R1 MID VO1P1 R_NOISELESS 4.63kJX_U32 VO1P1 MID MID VO1P2 AOL_GM1_V1 PARAMS: GAIN=1.2m IPOS=370u+ INEG=-370u#C_C21 MID IN+ 1p TC=0,0 #C_C22 IN- MID 1p TC=0,0 :X_U27 N3715438 0 LVDD 0 IQ_SRC PARAMS: GAIN=1E-3&R_R25 IN- IN+ R_NOISELESS 10G4R_R_MID2 N4052080 N4051938 R_NOISELESS 1MEG$X_U1 IN- IN+ VS+ VS- ESD_IN)C_C8 VO1P1 VO1P2 {CM3} TC=0,0 /R_R54 N3977925 VO1P1 R_NOISELESS {RZ2}+G_G_VSP_BUFFER1 VDD_LV 0 LVDD 0 -1KX_U30 IN+ 0 N3739136 0 N3739056 N3739216 VCM_CLAMP PARAMS: GAIN=1'R_R36 N3739136 0 R_NOISELESS 1(R_R_MID5 VDD_LV 0 R_NOISELESS 1*C_C9 VO1P2 N02244 {CM2} TC=0,0 &C_C25 0 N3739150 1p TC=0,0 PX_U18 LVSS VO1P3 0 VO1P1 AOL_GM1_V1 PARAMS: GAIN=-5.5m IPOS=0 INEG=-1m!E_E11 V_OUT 0 N04481 0 10R_R35 N3739136 N3739150 R_NOISELESS 100&C_C26 0 N4052080 1f TC=0,0 4R_R_MID3 N4051938 N4052120 R_NOISELESS 1MEG%X_H3 N04481 OUT VIMON 0 BE_v1_H3 +R_R_MID6 N4051938 0 R_NOISELESS 1T0.PARAM cm1=18p rnull=500 cm3=5p rz2=600 cm2=5p.ENDS".subckt GainStage_v1_S1 1 2 3 4 S_S1 3 4 1 2 _S1RS_S1 1 2 1G=.MODEL _S1 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S1".subckt GainStage_v1_S8 1 2 3 4 S_S8 3 4 1 2 _S8RS_S8 1 2 1G=.MODEL _S8 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S8".subckt GainStage_v1_S3 1 2 3 4 S_S3 3 4 1 2 _S3RS_S3 1 2 1G=.MODEL _S3 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S3#.subckt GainStage_v1_S10 1 2 3 4 S_S10 3 4 1 2 _S10RS_S10 1 2 1G>.MODEL _S10 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S10".subckt GainStage_v1_S7 1 2 3 4 S_S7 3 4 1 2 _S7RS_S7 1 2 1G=.MODEL _S7 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S7".subckt GainStage_v1_S6 1 2 3 4 S_S6 3 4 1 2 _S6RS_S6 1 2 1G=.MODEL _S6 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S6".subckt GainStage_v1_S4 1 2 3 4 S_S4 3 4 1 2 _S4RS_S4 1 2 1G=.MODEL _S4 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S4".subckt GainStage_v1_S2 1 2 3 4 S_S2 3 4 1 2 _S2RS_S2 1 2 1G=.MODEL _S2 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S2".subckt GainStage_v1_S5 1 2 3 4 S_S5 3 4 1 2 _S5RS_S5 1 2 1G=.MODEL _S5 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S5#.subckt GainStage_v1_S14 1 2 3 4 S_S14 3 4 1 2 _S14RS_S14 1 2 1G>.MODEL _S14 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S14#.subckt GainStage_v1_S16 1 2 3 4 S_S16 3 4 1 2 _S16RS_S16 1 2 1G>.MODEL _S16 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S16".subckt GainStage_v1_S9 1 2 3 4 S_S9 3 4 1 2 _S9RS_S9 1 2 1G=.MODEL _S9 VSWITCH Roff=1e6 Ron=1 Voff=0.0V Von=2.0V.ends GainStage_v1_S9#.subckt GainStage_v1_S13 1 2 3 4 S_S13 3 4 1 2 _S13RS_S13 1 2 1GE.MODEL _S13 VSWITCH Roff=1e12 Ron=2857.14 Voff=0.0V Von=2.0V.ends GainStage_v1_S13".subckt GainStage_v1_H1 1 2 3 4 H_H1 3 4 VH_H1 1VH_H1 1 2 0V.ends GainStage_v1_H1".subckt GainStage_v1_H2 1 2 3 4 H_H2 3 4 VH_H2 1VH_H2 1 2 0V.ends GainStage_v1_H2".subckt GainStage_v1_H3 1 2 3 4 H_H3 3 4 VH_H3 1VH_H3 1 2 0V.ends GainStage_v1_H3#.subckt GainStage_v1_S11 1 2 3 4 S_S11 3 4 1 2 _S11RS_S11 1 2 1GB.MODEL _S11 VSWITCH Roff=1e12 Ron=20e3 Voff=0.0V Von=2.0V.ends GainStage_v1_S11#.subckt GainStage_v1_S12 1 2 3 4 S_S12 3 4 1 2 _S12RS_S12 1 2 1GE.MODEL _S12 VSWITCH Roff=1e12 Ron=6.667e3 Voff=0.0V Von=2.0V.ends GainStage_v1_S12%.subckt Buffered_Switch_S1 1 2 3 4 S_S1 3 4 1 2 _S1RS_S1 1 2 1G8.MODEL _S1 VSWITCH Roff=1G Ron=1 Voff=0V Von=2V.ends Buffered_Switch_S1.subckt BE_v1_H1 1 2 3 4 H_H1 3 4 VH_H1 1VH_H1 1 2 0V.ends BE_v1_H1.subckt BE_v1_H3 1 2 3 4 H_H3 3 4 VH_H3 1VH_H3 1 2 0V.ends BE_v1_H3'* PSpice Model Editor - Version 17.4.0*$*$*4* PGA855 - Decoder Logic NMOS and PMOS Model calls.* Created Date: April 20, 2023(* Created Date: Srivatsan Sathyamoorthy** NMOSD.MODEL MND NMOS( VTO=0.714 XJ=1.7E-07 KP=200M GAMMA=0.035 PHI=0.65 @+ LAMBDA=0.02 TOX=100N RS=1 RD=1 RSH=3 CGDO=4P CGSO=4P CGBO=2P)* * PMOSD.MODEL MPD PMOS( VTO=0.714 XJ=1.7E-07 KP=200M GAMMA=0.035 PHI=0.65 @+ LAMBDA=0.02 TOX=100N RS=1 RD=1 RSH=3 CGDO=4P CGSO=4P CGBO=2P)**$*%* PSpice Model Editor - Version 17.4*$&.model R_NOISELESS RES(T_ABS=-273.15)*$E.subckt AOL_1 VC+ VC- IOUT+ IOUT- PARAMS: GAIN=1e-4 IPOS=.5 INEG=-.58G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}.ends*$*O.subckt AOL_2 VC+ VC- IOUT+ IOUT- PARAMS: GAIN=20.36e-3 IPOS=0.163 INEG=-0.1638G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}.ends*$:.subckt CLAMP_AMP_HI VC+ VC- VIN COM VO+ VO- PARAMS: G=10)* Output G(COM,0) when condition not metOGVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}OGVo- COM Vo- Value = {IF(V(VIN,COM)V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}OGVo- COM Vo- Value = {IF(V(VIN,COM).SUBCKT FEMT2 1 2 PARAMS: NLFF = 0.1 FLWF = 0.001 NVRF = 0.1'.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164} .PARAM RNVF={1.184*PWR(NVRF,2)}1.MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16 I1 0 7 10E-3 I2 0 8 10E-3 D1 7 0 DVNF D2 8 0 DVNFE1 3 6 7 8 {GLFF} R1 3 0 1E9 R2 3 0 1E9 R3 3 6 1E9E2 6 4 5 0 10R4 5 0 {RNVF}R5 5 0 {RNVF} R6 3 4 1E9 R7 4 0 1E9G1 1 2 3 4 1E-6 C1 1 0 1E-15 C2 2 0 1E-15 C3 1 2 1E-15.ENDS*$*M.subckt GR_SRC VC+ VC- IOUT+ IOUT- PARAMS: GAIN=1 IPOS=0.326e1 INEG=-0.326e18G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}.ends*$*5.subckt IQ_SRC VC+ VC- IOUT+ IOUT- PARAMS: GAIN=1e-3?G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,GAIN*V(VC+,VC-) )}.ends*$*!.subckt OL_SENSE COM SW+ OLN OLP * pins COM SW+ OLN OLPEGSW+ COM SW+ Value = {IF((V(OLN,COM)>10e-3 | V(OLP,COM)>10e-3),1,0)}.ends*$*$.subckt SW_OL SW_OL MID CAP_L CAP_R@.model OL_SW VSWITCH(Ron=1e-3 Roff=1e12 Von=900e-3 Voff=800e-3)S1 CAP_L CAP_R SW_OL MID OL_SW.ends*$*.subckt SW_OR CLAMP OLN OLP;.model OR_SW VSWITCH(Ron=10e-3 Roff=1e12 Vt=10e-3 Vh=1e-3)S1 OLP CLAMP CLAMP OLP OR_SWS2 CLAMP OLN OLN CLAMP OR_SW.ends*$*?.subckt VCM_CLAMP VIN+ VIN- IOUT- IOUT+ VP+ VP- PARAMS: GAIN=1IG1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}.ends*$*/.subckt VNSE1 1 2 PARAMS: FLW=1 NLF=120 NVR=18** VNSE1 - input voltage noise in nV/rt-Hz* Input variables* Set up 1/f noise* FLW = 1/f frequency in Hz* .param FLW=1<* NLF = voltage noise density at 1/f frequency in nV/rt(Hz)* .param NLF=18.131* Set up broadband noise5* NVR = broadband voltage noise density in nV/rt(Hz)* .param NVR=5.73* Calculated values$.param GLF={PWR(FLW,0.25)*NLF/1164}.param RNV={1.184*PWR(NVR,2)}/.model DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16* Circuit connections I1 0 7 10E-3 I2 0 8 10E-3 D1 7 0 DVN D2 8 0 DVNE1 3 6 7 8 {GLF} R1 3 0 1E9 R2 3 0 1E9 R3 3 6 1E9E2 6 4 5 0 10 R4 5 0 {RNV} R5 5 0 {RNV} R6 3 4 1E9 R7 4 0 1E9 E3 1 2 3 4 1.ends*$*!.subckt VNSE2 1 2 PARAMS: NVR=18*.param NVR=18.param RNV={1.184*PWR(NVR,2)}* Circuit connectionsE2 1 2 5 0 10 R4 5 0 {RNV} R5 5 0 {RNV}.ends*$*B.subckt VOS_DRIFT VOS+ VOS- PARAMS: DC=496.4e-6 POL=1 DRIFT=2E-06,E1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)}.ends*$*M.subckt ZO_SRC VC+ VC- IOUT+ IOUT- PARAMS: GAIN=200 IPOS=14.5e5 INEG=-14.5e58G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}.ends*$#.subckt V_Compare COM SW+ OLN OLP9ESW+ SW+ COM Value = {IF(V(OLN,COM)>V(OLP,COM),10E-3,0)}.ends**$%* PSpice Model Editor - Version 17.4*$J.subckt AOL_GM1_v1 VC+ VC- IOUT+ IOUT- PARAMS: GAIN=1e-4 IPOS=.5 INEG=-.58G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}.ends*$(** PSpice Model Editor - Version 17.4.0*$*c.SUBCKT AOL_GM2_V2 IMON VOUT MID IN+ IN- OUT+ OUT- PARAMS: GM2_NO_IOUT=-17m K=1 IPOS=10m INEG=-10m**$&.model R_NOISELESS RES(T_ABS=-273.15)** Get output from AOL_GM1_V1G1 N1 IN- IN+ IN- -1R1 N1 IN- R_NOISELESS 1*&* Get Output current as voltage inputG2 N2 MID IMON MID -1R2 N2 MID R_NOISELESS 1*5* Get Output voltage as voltage input through bufferG2B N3 MID VOUT MID -1R2B N3 MID R_NOISELESS 1*;* Make GM2 as a function of IOUT (VIMON) and VOUT (VOUT_S)*/* Set Claw resistance based on ISC and VSUPPLY.PARAM RCLAW_NEG = 350.0.PARAM RCLAW_POS = 350.0* =* Set MAX and MIN for INEG and IPOS based on the calculation .PARAM IPOS_ISCLIMIT = { IPOS } .PARAM INEG_ISCLIMIT = { INEG }*DG3 OUT+ OUT- VALUE={LIMIT(((-GM2_NO_IOUT + K*ABS(V(N2))) * -V(N1)),S+ MAX( (MAX(INEG, (INEG - ((V(N3) + ABS(V(MID))) / RCLAW_NEG)))), INEG_ISCLIMIT ),R+ MIN( (MIN(IPOS, (IPOS - ((V(N3) - ABS(V(MID))) / RCLAW_POS)))), IPOS_ISCLIMIT )+)}.ENDS AOL_GM2_V2**$A0A1A2DA_IN+DA_IN-DGNDINNINPLVDDLVSSOUTREFVS+VS-DB@h VPT_0F8A8AC020251210162850Battery_9V_V (V)2@DB VNT_0F8A84E020251210162850Battery_9V_V (V)2@BpVCVS1T_0F8A7F0020251210162850?BpXVCVS2T_0F8A792020251210162850BV_INT_0F8A734020251210162850 Sgen (VG){Gz??@@VDBP VICMT_0F8A6D6020251210162850Battery_9V_V (V)DB VA2T_0F8A678020251210162850Battery_9V_V (V)DB VA1T_0F8A61A020251210162850Battery_9V_V (V)@DB VA0T_0F8A5BC020251210162850Battery_9V_V (V)@DBh LVDDT_0E68D1C020251210162850Battery_9V_V (V)@DB LVSST_0E68CBE020251210162850Battery_9V_V (V)DBx V_REFT_0E68C60020251210162850Battery_9V_V (V)@ B0R1T_0E68C02020251210162850R_AX600_W200 (R)@@?Y@ B0C1T_0E68BA4020251210162850CP_CYL300_D700_L1400 (C) dy=@eAY@?Br8VOUTT_0E68B46020251210162850 NOPCB (VF)"Br VOST_0E68AE8020251210162850 Vmet (VM)BpDAIN+T_0F8A968020251210162850 NOPCB (J)BpHDAIN-T_0F8A90A020251210162850 NOPCB (J)BfT_0F8AEEA020251210162850 NOPCB (GND)BfT_0F8AE8C020251210162850 NOPCB (GND)Bf T_0F8AE2E020251210162850 NOPCB (GND)BfXT_0F8ADD0020251210162850 NOPCB (GND)BfPT_0F8AD72020251210162850 NOPCB (GND)BfT_0F8AD14020251210162850 NOPCB (GND)BfT_0F8ACB6020251210162850 NOPCB (GND)Bf(T_0F8AC58020251210162850 NOPCB (GND)BfXT_0F8ABFA020251210162850 NOPCB (GND)BfT_0F8AB9C020251210162850 NOPCB (GND)Bf T_0F8AB3E020251210162850 NOPCB (GND)BfT_0F8AAE0020251210162850 NOPCB (GND)BfhT_0F8AA82020251210162850 NOPCB (GND)BfhT_0F8AA24020251210162850 NOPCB (GND)BfT_0F8A9C6020251210162850 NOPCB (GND)8?+ ]@"MbP??ư>'dd?Y@[dddd$@?.A.A.AeAMbP?@@?~jth?ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .>#i;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+= _BKH9$@Y@& .>ư>?.AMbP??????I@Default analysis parameters. These parameters establish convergence and sufficient accuracy for most circuits. In case of convergence or accuracy problems click on the "hand " button to Open other parameter sets.?Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%ITNoname