OBSSk Spice MacroV1.00 98/01/15%TINA Device Editor 9.3.200.277 SF-TI Copyright 1997 DesignSoft, Inc. 'LMH7324LMH7324SC:\Users\a0227287\AppData\Local\Temp\DesignSoft\{Tina9-TI-01072020-103954}\LMH7324SCK#LMH7324Label°ÿØÿP(¸ÿØÿH(X0¼ÿÉÿd*IN->=V(2)),V(VSS °ÿøÿ @d*Q1)>V(2)-1M),V(V °ÿ @d*QBARD 0 VALUE =  °ÿ @d*IN+IN,COM),V(VCC °ÿèÿ @d*VCCIßD¸6 Pðÿ @d*VCCO P @d*VEE P @f¸ÿØÿH(€ÿÿg"LMH7324Arialåÿøÿ333333ó?€öx\VÙvå@öx\VÙvå@ð* source LMH7324'* PSpice Model Editor - Version 17.2.0*$ * LMH7324N*****************************************************************************J* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedH** or implied, with respect to this model, including the warranties of F** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality)** and performance is with the customer.N******************************************************************************D* This model is subject to change without notice. Texas Instruments:* Incorporated is not responsible for updating this model*N******************************************************************************'** Released by: Texas Instruments Inc.* Part: LMH7324* Date: 04/30/2020* Model Type: All In One* Simulator: PSPICE !* Simulator Version: 17.2.0.p001* EVM Order Number: N/A * EVM Users Guide: N/A '* Datasheet: SNOSAZ2G - September 2007* Model Version: 1.0*N****************************************************************************** * Updates:** Version 1.0 : Release to Web&* 2.0 : Improving Convergence*N***************************************************************************** * Notes:)* The following parameters are modeled: (* Iq, tpd, Ibias, Vcm, Vs, tr, tf, Vhysb* If the input or supply rail goes beyond the abs max limits, the output will float at mid supplyW* If both inputs go beyond the commmon mode limit, the output will float at mid supply[* If one input goes beyond the commmon mode limit, the output will reflect the input state** Modeled based off of 12V EC table specsN*****************************************************************************/.SUBCKT LMH7324 IN+ IN- Q QBAR VCCI VCCO VEE /X_U1 IN+ IN- Q QBAR VCCI VCCO VEE SCHEMATIC1 .ENDS /.SUBCKT LMH7324 IN+ IN- Q QBAR VCCI VCCO VEE /X_U1 IN+ IN- Q QBAR VCCI VCCI VEE SCHEMATIC1 V_V3 VEE 0 -6V_V2 VCCI 0 6V_V6 IN- 0 0V_V7 IN+ 0 +SIN 0 100m 100e6 0 0 0.ENDS 2.SUBCKT SCHEMATIC1 IN+ IN- Q QBAR VCCI VCCO VEE $E_E2 N734689 0 COMP_OUT 0 11X_U12 IN+_B IN-_B IN_CM_EN VCCI VEE VinCMRange I_I1 VCCI 0 DC 5.6m =X_U23 VCCO N737342 OUT_VCM PARAMS: HIGH=0.8 LOW=1.41X_U14 VCCO_EN VCCI_B VCCO_B VEE_B SupplyEnable %E_E1 N734637 0 N734345 OUT 1"E_E5 OUT1 0 OUT N737342 1=X_U22 VCCO N734715 OUT_VCM PARAMS: HIGH=0.8 LOW=1.4@X_U8 IN+_B IN-_B COMP_OUT N734273 0 N736474 HPA_COMPHYS/X_U10 IN+ IN- IN+_B IN-_B INPUT_BUFFER=X_U3 VCCI VCCO VEE VCCI_B VCCO_B VEE_B SUPPLY_BUFFER1X_U15 VCCI_EN VCCI_B VCCI_B VEE_B SupplyEnable X_U17 N734689 OUT Delay 9X_U19 VCCX_EN IN_EN VCCI VEE OUT2 QBAR OUTPUT_ENV_V15 N734273 0 .358X_U21 VCCI_EN VCCO_EN VCCX_EN VCCI VEE ANDGATEV_V12 N734345 0 .35V_V18 N736474 0 20.8mI_I2 VCCO 0 DC 11.6m &E_E3 OUT2 0 N734637 N734715 19X_U20 IN_CM_EN IN_ABS_EN IN_EN VCCI VEE ANDGATE6X_U18 VCCX_EN IN_EN VCCI VEE OUT1 Q OUTPUT_EN0X_U24 IN+_B IN-_B IN_ABS_EN VCCI VEE VinRange !E_E6 N786624 0 IN+ IN- 1.X_U25 N786624 N789154 N789745 IB_LUT .X_F1 N789154 0 N7889552 IN+ SCHEMATIC1_F1 #R_R1 0 N7889552 1 TC=0,0 #R_R2 0 N7894982 1 TC=0,0 .X_F2 N789745 0 N7894982 IN- SCHEMATIC1_F2 .ENDS ,.SUBCKT VinRange INN INP INRANGE VCCI VEE 8X_U5 N735214 N735256 N735232 VCCI VEE VCC_RANGEV_V1 N735214 0 139X_U15 N735256 N735428 N735366 VCCI VEE VCC_Range2X_U13 INP INN N735256 VCCI VEE DIFFERENCEV_V2 N735428 0 -138X_U16 N735232 N735366 INRANGE VCCI VEE ANDGATE.ENDS .SUBCKT Delay VIN VOUT #E_E2 N669175 0 N668473 0 1.T_T1 N669175 0 VOUT 0 Z0=50 TD=596p !R_R14 0 VOUT 50 TC=0,0 $C_C6 0 N668473 1p TC=0,0 (R_R13 VIN N668473 38.4 TC=0,0 .ENDS (.SUBCKT SupplyEnable EN VCCI VCCX VEE 8X_U5 N682350 N682386 N682362 VCCI VEE VCC_RANGE3X_U15 N682386 0 N682496 VCCI VEE VCC_Range3X_U13 VCCX VEE N682386 VCCI VEE DIFFERENCE3X_U16 N682362 N682496 EN VCCI VEE ANDGATEV_V1 N682350 0 13.2.ENDS ..SUBCKT VinCMRange INN INP INRANGE VCCI VEE V_V12 N39616 VCCI -2V_V11 N39882 VEE 0V_V4 N40308 VEE 0V_V3 N40056 VCCI -23X_U21 INP N39882 N39788 VCCI VEE VCC_RANGE5X_U24 N39678 N39788 N39772 VCCI VEE ANDGATE2X_U5 N39616 INP N39678 VCCI VEE VCC_RANGE4X_U18 N39772 N40012 INRANGE VCCI VEE ORGATE3X_U23 INN N40308 N40218 VCCI VEE VCC_RANGE3X_U22 N40056 INN N40118 VCCI VEE VCC_RANGE5X_U25 N40118 N40218 N40012 VCCI VEE ANDGATE.ENDS .subckt SCHEMATIC1_F1 1 2 3 4 F_F1 3 4 VF_F1 1VF_F1 1 2 0V.ends SCHEMATIC1_F1 .subckt SCHEMATIC1_F2 1 2 3 4 F_F2 3 4 VF_F2 1VF_F2 1 2 0V.ends SCHEMATIC1_F2.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS$.SUBCKT Difference 1 2 OUT VDD VSS !EOUT OUT 0 VALUE = { V(1)- V(2)} R1 OUT 2 1 C1 2 0 1e-12.ENDS1.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }bEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS.SUBCKT HYS_RES 1 OUT :ERHYS RHYS 0 VALUE = {((1000*V(1))/(1000*1 - V(1)))/1000}:*EOUT OUT 0 VALUE = { ((1000*V(1))/(1000*1 - V(1)))/1000} EOUT OUT 0 VALUE = {IF ((V(1)<= 1000 & V(1) >= 999.9) , 0 , LIMIT ((.4**(.25*V(RHYS))*42 + .9**(.3*(V(RHYS)-4))*2 + .5**(.07*(V(RHYS)+3))*8)*.001, 51.1858,0))}.ENDS!.SUBCKT INPUT_BUFFER 1 2 INP INNEINP_NEW INP 0 VALUE = {V(1)}EINN_NEW INN 0 VALUE = {V(2)}.ENDS.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSSeEOUT OUT 0 VALUE = { IF( ((V(1) < (V(VDD)+V(VSS))/2 ) & (V(2) < (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS+.SUBCKT SUPPLY_BUFFER 1 2 3 VCCI VCCO VEE EVCCI_NEW VCCI 0 VALUE = {V(1)} EVCCO_NEW VCCO 0 VALUE = {V(2)}EVEE_NEW VEE 0 VALUE = {V(3)} C1 3 0 1e-12.ENDS.SUBCKT SWITCH_EN 1 2 LATCH EN + params: + high = 0.8 + low = 1.4YE1 EN 0 VALUE = { IF( ((V(LATCH) >= (V(2) + low)) & (V(LATCH)<= (V(1) -high))), 0, 1 ) }.ENDS#.SUBCKT VCC_Range 1 2 OUT VDD VSS BEOUT OUT 0 VALUE = { IF( ( V(1) > V(2) - 1m ), V(VDD), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS >EOUT OUT 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS..SUBCKT OUTPUT_EN VS_EN IN_EN VCCI VEE IN OUT0EVMID VMID 0 VALUE = { ( V(VCCI) + V(VEE) )/2 }^EOUT OUT 0 VALUE = { IF( ((V(VS_EN)> V(VMID) ) & (V(IN_EN) > (V(VMID) ))), V(IN), V(VMID) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS.SUBCKT OUT_VCM VCCO OUT@EVMID VMID 0 VALUE = { (( V(VCCO) - 1.15) + (V(VCCO) - 1.5))/2})EOUT OUT 0 VALUE = { -1*(V(VMID)-.35/2)} R1 OUT 2 1 C1 2 0 1e-12.ENDS.subckt VLIM IN COM VO VCCOCGVO COM VO Value = {LIMIT(V(IN,COM),V(VCCO) - 1.15,V(VCCO) - 1.5)} RVO COM VO 1.ENDS.SUBCKT IB_LUT IN IOUT+ IOUT- :E1 lmp 0 VALUE = {(6.916666667*V(IN) - 1.383333333)*1e-6};E2 lmn 0 VALUE = {(-6.916666667*V(IN) - 2.766666667)*1e-6}:E3 ln 0 VALUE = {(-0.114583333*V(IN) - 4.127083333)*1e-6}9E4 lp 0 VALUE = {(0.119565217*V(IN) - 4.102173913)*1e-6}`G1 IOUT+ 0 VALUE = {IF(V(IN)<-.4,V(lp),IF(V(IN)>-.4001 & V(IN)<.2001,V(lmp),IF(V(IN)>.2,0,0)))}`G2 IOUT- 0 VALUE = {IF(V(IN)<-.4,0,IF(V(IN)>-.4001 & V(IN)<.2001,V(lmn),IF(V(IN)>.2,V(ln),0)))}.ENDSIN-QQBARIN+VCCIVCCOVEEÿÿ