8.3.1 Battery Voltage Regulation

The bq24616 uses a high-accuracy voltage band gap and regulator for high charging-voltage accuracy. The charge voltage is programmed through a resistor-divider from the battery to ground, with the midpoint tied to the VFB pin. The voltage at the VFB pin is regulated to 2.1 V in the 0°C to 45°C range, giving the following equation for the regulation voltage:

Equation 1.

where

• R2 is connected from VFB to the battery and R1 is connected from VFB to GND.

8.3.2 Battery Current Regulation

The ISET1 input sets the maximum fast-charging current in the 10°C–60°C range. Battery-charge current is sensed by resistor R_SR, connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 10-mΩ sense resistor, the maximum charging current is 10 A. The equation for charge current is:

Equation 2.

V_ISET1, the input voltage range of ISET1, is from 0 V to 2 V. The SRP and SRN pins are used to sense voltage across R_SR with default value of 10 mΩ; however, resistors of other values can also be used. A larger sense resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher conduction loss.

8.3.3 Input Adapter Current Regulation

The total input from an AC adapter or other DC source is a function of the system supply current and the battery charging current. System current normally fluctuates as portions of the systems are powered up or down. Without dynamic power management (DPM), the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using DPM, the battery charger reduces the charging current when the input current exceeds the input current limit set by ACSET. The current capability of the AC adaptor can be lowered, reducing system cost.

Similar to setting battery regulation current, adaptor current is sensed by resistor R_AC connected between ACP and ACN. Its maximum value is set by ACSET using Equation 3:

Equation 3.

V_ACSET, the input voltage range of ACSET, is from 0 to 2 V. The ACP and ACN pins are used to sense voltage across R_AC with a default value of 10 mΩ; however, resistors of other values can also be used. A larger sense resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher conduction loss.

8.3.4 Precharge

On power up, if the battery voltage is below the V_LOWV threshold, the bq24616 applies the precharge current to the battery. This feature is intended to revive deeply discharged cells. If the V_LOWV threshold is not reached within 30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.

The precharge current (I_PRECHARGE) is determined by the voltage on the ISET2 pin (V_ISET2) according to Equation 4.

Equation 4.

8.3.5 Charge Termination, Recharge, and Safety Timer

The bq24616 monitors the charging current during the voltage regulation phase. When V_TTC is valid, termination is detected while the voltage on the VFB pin is higher than the V_RECH threshold AND the charge current is less than the I_TERM threshold, as calculated in Equation 5:

Equation 5.

V_ISET2, the input voltage of ISET2, is from 0 to 2 V. The minimum precharge and termination current is clamped to be around 125 mA with default 10-mΩ sensing resistor. As a safety backup, the bq24616 also provides a programmable charge timer. The charge time is programmed by the capacitor connected between the TTC pin and GND, and is given by Equation 6

Equation 6.

where

• C_TTC (range from 0.01 µF to 0.11 µF to give 1-h to 10-h safety time) is the capacitor connected from the TTC pin to GND.
• K_TTC is the constant multiplier (5.6 min/nF).

A new charge cycle is initiated and the fast-charge safety timer is reset when one of the following conditions occurs:

• The battery voltage falls below the recharge threshold.
• A power-on-reset (POR) event occurs.
• CE is toggled.

The TTC pin may be taken LOW to disable termination and to disable the safety timer. If TTC is pulled to VREF, the bq24616 continues to allow termination but disables the safety timer. TTC taken low resets the safety timer. When ACOV, VCCLOWV, and SLEEP mode resume normal, the safety timer also is reset.

8.3.6 Power Up

The bq24616 uses a SLEEP comparator to determine the source of power on the VCC pin, because VCC can be supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, the bq24616 enables the ACFET and disables BATFET. If all other conditions are met for charging, the bq24616 then attempts to charge the battery (see Enable and Disable Charging). If the SRN voltage is greater than VCC, indicating that the battery is the power source, the bq24616 enables BATFET, and enters a low-quiescent-current (<15-μA) SLEEP mode to minimize current drain from the battery.

If VCC is below the UVLO threshold, the device is disabled, ACFET turns of, and BATFET turns on.

8.3.7 Enable and Disable Charging

The following conditions must be valid before charge is enabled:

• CE is HIGH.
• The device is not in UVCCLOWV mode.
• The device is not in SLEEP mode.
• The VCC voltage is lower than the ac overvoltage threshold (VCC < V_ACOV).
• 30-ms delay is complete after initial power up.
• The REGN LDO and VREF LDO voltages are at the correct levels.
• Thermal shut (TSHUT) is not valid.
• TS fault is not detected.

Any of the following conditions stops ongoing charging:

• CE is LOW.
• Adapter is removed, causing the device to enter VCCLOWV or SLEEP mode.
• Adapter is over voltage.
• The REGN or VREF LDOs are overloaded.
• TSHUT IC temperature threshold is reached (145°C on rising edge with 15°C hysteresis).
• TS voltage goes out of range, indicating the battery temperature is too hot or too cold.
• TTC safety timer times out.

8.3.8 System Power Selector

The bq24616 automatically switches adapter or battery power to the system load. The battery is connected to the system by default during power up or during SLEEP mode. The battery is disconnected from the system and then the adapter is connected to the system 30 ms after exiting SLEEP. An automatic break-before-make logic prevents shoot-through currents when the selectors switch.

ACDRV is used to drive a pair of back-to-back P-channel power MOSFETs between the adapter and ACP with sources connected together and to VCC. The FET connected to the adapter prevents reverse discharge from the battery to the adapter when turned off. The P-channel FET with the drain connected to the adapter input provides reverse battery discharge protection when off, and also minimizes system power dissipation with its low r_DS(on) compared to a Schottky diode. The other P-channel FET connected to ACP separates the battery from the adapter, and provides a limited dI/dt when connecting the adapter to the system by controlling the FET turnon time. The BATDRV controls a P-channel power MOSFET placed between BAT and the system.

When the adapter is not detected, ACDRV is pulled to VCC to keep ACFET off, disconnecting the adapter from the system. BATDRV stays at ACN-6 V to connect the battery to the system.

Approximately 30 ms after the device comes out of SLEEP mode, the system begins to switch from battery to adapter. The break-before-make logic keeps both ACFET and BATFET off for 10 µs before ACFET turns on. This prevents shoot-through current or any large discharging current from going into the battery. BATDRV is pulled up to ACN and the ACDRV pin is set to VCC-6 V by an internal regulator to turn on P-channel ACFET, connecting the adapter to the system.

When the adapter is removed, the system waits until VCC drops back to within 200 mV above SRN to switch from the adapter back to the battery. The break-before-make logic still keeps 10-μs dead time. The ACDRV is pulled up to VCC and the BATDRV pin is set to ACN-6 V by an internal regulator to turn on P-channel BATFET, connecting the battery to the system.

Asymmetrical gate drive (fast turnoff and slow turnon) for the ACDRV and BATDRV drivers provides fast turnoff and slow turnon of the ACFET and BATFET to help the break-before-make logic and to allow a soft start at turnon of either FET. The soft-start time can be further increased by putting a capacitor from gate to source of the P-channel power MOSFETs.

8.3.9 Automatic Internal Soft-Start Charger Current

The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of stepping up the charge regulation current in eight evenly divided steps up to the programmed charge current. Each step lasts around 1.6 ms, for a typical rise time of 12.8 ms. No external components are needed for this function.

8.3.10 Converter Operation

The synchronous buck PWM converter uses a fixed-frequency voltage mode with a feed-forward control scheme. A type-III compensation network allows using ceramic capacitors at the output of the converter. The compensation input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 12 kHz to 17 kHz for the bq24616, where the resonant frequency, f_o, is given by:

Equation 7.

An internal sawtooth ramp is compared to the internal EAO error-control signal to vary the duty cycle of the converter. The ramp height is 7% of the input adapter voltage, making it always directly proportional to the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage and simplifies the loop compensation. The ramp is offset by 300 mV in order to allow zero-percent duty cycle when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to get a 100% duty-cycle PWM request. Internal gate-drive logic allows achieving 99.5% duty cycle while ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2 V for more than 3 cycles, then the high-side N-channel power MOSFET is turned off and the low-side N-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again due to leakage current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.

The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping the switching frequency out of the audible noise region. Also see Application and Implementation for how to select the inductor, capacitor and MOSFET.

8.3.11 Synchronous and Nonsynchronous Operation

The charger operates in synchronous mode when the SRP-SRN voltage is above 5 mV (0.5-A inductor current for a 10-mΩ sense resistor). During synchronous mode, the internal gate-drive logic ensures there is break-before-make complementary switching to prevent shoot-through currents. During the 30-ns dead time where both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the low-side FET turn on keeps the power dissipation low and allows safely charging at high currents. During synchronous mode, the inductor current is always flowing and the converter operates in continuous-conduction mode (CCM), creating a fixed two-pole system.

The charger operates in nonsynchronous mode when the SRP-SRN voltage is below 5 mV (0.5-A inductor current for a 10-mΩ sense resistor). The charger is forced into nonsynchronous mode when the battery voltage is lower than 2 V or when the average SRP-SRN voltage is lower than 1.25 mV.

During nonsynchronous operation, the body diode of the lower-side MOSFET can conduct the positive inductor current after the high-side N-channel power MOSFET turns off. When the load current decreases and the inductor current drops to zero, the body diode is naturally turned off and the inductor current becomes discontinuous. This mode is called discontinuous-conduction mode (DCM). During DCM, the low-side N-channel power MOSFET turns on for around 80 ns when the bootstrap capacitor voltage drops below 4.2 V; then the low-side power MOSFET turns off and stays off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. The 80-ns low-side MOSFET ON-time is required to ensure the bootstrap capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for battery chargers, where unlike regular DC-DC converters, there is a battery load that maintains a voltage and can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high- and low-side MOSFETs) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After 80-ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring.

At very low currents during nonsynchronous operation, there may be a small amount of negative inductor current during the 80-ns recharge pulse. The charge should be low enough to be absorbed by the input capacitance. Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (only 80-ns recharge pulse) either, and there is almost no discharge from the battery.

During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole is proportional to the load current, because the converter does not sink current, and only the load provides a current sink. This means at very low currents the loop response is slower, as there is less sinking current available to discharge the output voltage.

8.3.12 Cycle-by-Cycle Charge Undercurrent Protection

If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into nonsynchronous mode when the average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the switching cycle to prevent negative inductor current. During DCM, the low-side FET only turns on for at around 80 ns to provide refresh charge for the bootstrap capacitor when the bootstrap capacitor voltage drops below 4.2 V. This is important to prevent negative inductor current from causing a boost effect in which the input voltage increases as power is transferred from the battery to the input capacitors and leads to an overvoltage stress on the VCC node and potentially causes damage to the system.

8.3.13 Input Overvoltage Protection (ACOV)

ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage reaches the ACOV threshold, charge is disabled and the system is switched to the battery instead of the adapter.

8.3.14 Input Undervoltage Lockout (UVLO)

The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from either the input adapter or the battery, because a conduction path exists from the battery to VCC through the high-side NMOS body diode. When VCC is below the UVLO threshold, all circuits on the IC are disabled, and the gate-drive bias to ACFET and BATFET is disabled. ACFET is OFF and BATFET is ON.

8.3.15 Battery Overvoltage Protection

The converter does not allow the high-side FET to turn on until the BAT voltage goes below 102% of the regulation voltage. This allows one-cycle response to an overvoltage condition, such as occurs when the load is removed or the battery is disconnected. An 8-mA current sink from SRP/SRN to GND is on only during charge and allows discharging the stored output inductor energy that is transferred to the output capacitors. BATOVP also suspends the safety timer.

8.3.16 Cycle-by-Cycle Charge Overcurrent Protection

The charger has secondary cycle-to-cycle overcurrent protection. It monitors the charge current, and prevents the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off when the overcurrent is detected, and automatically resumes when the current falls below the overcurrent threshold.

8.3.17 Thermal Shutdown Protection

The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junctions temperatures low. As an added level of protection, the charger converter turns off and self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off until the junction temperature falls below 130°C, then the charger soft-starts again if all other enable charge conditions are valid. Thermal shutdown also suspends the safety timer.

8.3.18 Temperature Qualification and JEITA Guideline

The controller continuously monitors battery temperature by measuring the voltage between the TS pin and GND. A negative-temperature-coefficient (NTC) thermistor and an external voltage divider typically develop this voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the voltage on the TS pin must be within the V_T1 to V_T5 thresholds. If V_TS is outside of this range, the controller suspends charge and waits until the battery temperature is within the V_T1 to V_T5 range. During the charge cycle, the battery temperature must be within the V_T1 to V_T5 thresholds. If battery temperature is outside of this range, the controller suspends charge and waits until the battery temperature is within the V_T1 to V_T5 range. The controller suspends charge by turning off the PWM charge FETs. If V_TS is within the range of V_T1 and V_T2, charge voltage regulation on V_FB pin is 2.1 V and the charge current is reduced to I_CHARGE/2 (to avoid early termination during V_T1 and V_T2 range, fast-charge current must be higher than 2 times the termination current); if V_TS is within the range of V_T2 and V_T3, the charge voltage regulation on V_FB pin is 2.1 V; if V_TS is within V_T3 and V_T4, the charge voltage regulation on V_FB pin is reduced back to 2.05 V; and if V_TS is within V_T4 and V_T5, the charge voltage regulation on the V_FB pin is further reduced to 2.025 V. Figure 13 summarizes the operation. See the Li-ion Battery-Charger Solutions for JEITA Compliance journal article (SLYT365).

Figure 13. Thermistor Sense Thresholds

Assuming a 103AT NTC thermistor on the battery pack as shown in , the values of RT1 and RT2 can be determined by using the following equations:

Equation 8.

Equation 9.

Figure 14. TS Resistor Network

For example, 103AT NTC thermistors are used to monitor the battery pack temperature. Selecting T1 = 0ºC for COLD and T5 = 60ºC for HOT results in R_T2 = 6.8 kΩ and R_T1 = 2.2 kΩ as calculated in the bq246xx Calculation Tool, available in the Tools & Software section of the product folder. A small RC filter is suggested to use for system-level ESD protection.

8.3.19 Timer Fault Recovery

The bq24616 provides a recovery method to deal with timer fault conditions. The following summarizes this method:

Condition 1: The battery voltage is above the recharge threshold and a time-out fault occurs.

Recovery Method: The timer fault clears when the battery voltage falls below the recharge threshold, and battery detection begins. A POR condition or taking CE low also clears the fault.

Condition 2: The battery voltage is below the recharge threshold and a time-out fault occurs.

Recovery Method: Under this scenario, the bq24616 applies the I_FAULT current to the battery. This small current is used to detect a battery-removal condition and remains on as long as the battery voltage stays below the recharge threshold. If the battery voltage goes above the recharge threshold, the bq24616 disables the fault current and executes the recovery method described in Condition 1. A POR condition or taking CE low also clears the fault.

8.3.20 PG Output

The open-drain PG (power-good) output indicates whether the VCC voltage is valid or not. The open-drain FET turns on whenever bq24616 has a valid VCC input (not in UVLO or ACOV or SLEEP mode). The PG pin can be used to drive an LED or communicate to the host processor.

8.3.21 CE (Charge Enable)

The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables charge, provided all the other conditions for charge are met (see Enable and Disable Charging). A high-to-low transition on this pin also resets all timers and fault conditions. There is an internal 1-MΩ pulldown resistor on the CE pin, so if CE is floated, the charge does not turn on.

8.3.22 Charge Status Outputs

The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in the Table 2. These status pins can be used to drive LEDs or communicate with the host processor. Note that OFF indicates that the open-drain transistor is turned off.

8.3.23 Battery Detection

For applications with removable battery packs, the bq24616 provides a battery-absent detection scheme to detect insertion or removal of battery packs reliably.

Figure 15. Battery Detection Flow Chart

Once the device has powered up, an 8-mA discharge current is applied to the SRN terminal. If the battery voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is turned on at low charge current (125 mA). If the battery voltage goes above the recharge threshold within 500 ms, there is no battery present and the cycle restarts. If either the 500-ms or 1-second timer times out before its respective threshold is hit, a battery is detected and a charge cycle is initiated.

Figure 16. Battery-Detect Timing Diagram

Care must be taken that the total output capacitance at the battery node is not so large that the discharge current source cannot pull the voltage below the LOWV threshold during the 1-second discharge time. The maximum output capacitance can be calculated as follows:

Equation 10.

where

• C_MAX is the maximum output capacitance.
• I_DISCH is the discharge current.
• t_DISCH is the discharge time.
• R₂ and R₁ are the voltage feedback resistors from the battery to the VFB pin.

The 0.5 factor is the difference between the RECHARGE and the LOWV thresholds at the VFB pin.

Example

For a 3-cell Li+ charger, with R2 = 500 kΩ, R1 = 100 kΩ (giving 12.6 V for voltage regulation), I_DISCH = 8 mA, t_DISCH = 1 s,

Equation 11.

Based on these calculations, no more than 2.7 mF should be allowed on the battery node for proper operation of the battery-detection circuit.