8.3.1 Automatic Internal Soft-Start Charger Current

Every time charge is enabled, the charger automatically applies soft-start on charge current to avoid any overshoot or stress on the output capacitors or the power converter. The charge current starts at 128 mA, and the step size is 64 mA in CCM mode for a 10-mΩ current sensing resistor. Each step lasts around 240 µs in CCM mode, until it reaches the programmed charge current limit. No external components are needed for this function. During DCM mode, the soft-start current step size is larger and each step lasts for a longer time period due to the intrinsic slow response of DCM mode.

8.3.2 High-Accuracy Current-Sense Amplifier

As an industry standard, a high-accuracy current-sense amplifier (CSA) is used to monitor the input current or the charge current, selectable through SMBus (ChargeOption() bit[5] = 0 selects the input current, bit[5] = 1 selects the charge current) by the host. The CSA senses voltage across the sense resistor by a factor of 20 through the IOUT pin. Once VCC is above UVLO and ACDET is above 0.6 V, CSA turns on and the IOUT output becomes valid. To lower the voltage on current monitoring, a resistor divider from IOUT to GND can be used and accuracy over temperature can still be achieved.

A 100-pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Adding filtering also adds additional response delay.

8.3.3 Charge Timeout

The IC includes a watchdog timer to terminate charging if the charger does not receive a write ChargeVoltage() or write ChargeCurrent() command within 175 s (adjustable through ChargeOption() command). If a watchdog timeout occurs, all register values stay unchanged, but charge is suspended. Write ChargeVoltage() or write ChargeCurrent() commands must be re-sent to reset the watchdog timer and resume charging. The watchdog timer can be disabled, or set to 44 s, 88 s, or 175 s through a SMBus command (ChargeOption() bit[14:13]). After watchdog timeout, write ChargeOption() bit[14:13] to disable the watchdog timer and also resume charging.

8.3.4 Input Overcurrent Protection (ACOC)

The IC cannot maintain the input current level if the charge current has been already reduced to zero. After the system current continues increasing to the 1.66× of input current DAC set point (with 2.5-ms blankout time), IFAULT is pulled to low and the charge is disabled for 1.3 s and will soft start again for charge if ACOC condition goes away. If such failure is detected seven times in 90 seconds, charge will be latched off and an adapter removal and system shutdown (make ACDET < 0.6 mV to reset IC) is required to start charge again. After 90 seconds, the failure counter will be reset to zero to prevent latch off.

The ACOC function can be disabled or the threshold can be set to 1.33×, 1.66× or 2.22× of input DPM current through SMBus command (ChargeOption() bit [2:1]).

8.3.5 Charge Overcurrent Protection (CHGOCP)

The IC has a cycle-by-cycle peak overcurrent protection. It monitors the voltage across SRP and SRN, and prevents the current from exceeding of the threshold based on the DAC charge current set point. The high-side gate drive turns off for the rest of the cycle when the overcurrent is detected, and resumes when the next cycle starts.

The charge OCP threshold is automatically set to 6 A, 9 A, and 12 A on a 10-mΩ current-sensing resistor based on charge current register value. This prevents the threshold to be too high which is not safe or too low which can be triggered in normal operation. Proper inductance should be selected to prevent OCP triggered in normal operation due to high inductor current ripple.

8.3.6 Battery Overvoltage Protection (BATOVP)

The IC will not allow the high-side and low-side FET to turn-on when the battery voltage at SRN exceeds 104% of the regulation voltage set-point. If BATOVP last over 30 ms, charger is completely disabled. This allows quick response to an overvoltage condition – such as occurs when the load is removed or the battery is disconnected. A 4-mA current sink from SRN to GND is on only during BATOVP and allows discharging the stored output inductor energy that is transferred to the output capacitors.

Some battery pack gas gauges will set the ChargeVoltage() and ChargeCurrent() registers to 0 V and 0 A after the battery pack is fully charged. If the ChargeVoltage() register is set to 0 V, the bq24707 triggers BATOVP, and the 4-mA current discharges the battery pack. The recommendation for bq24707 is to set the ChargeVoltage() register to full scale charge voltage (12.592 V for 3-S battery for example) after the battery is fully charged. The bq24707A will not trigger BATOVP, and there is no 4-mA current to discharge the battery pack if the ChargeVoltage() register is set 0 V. The recommendation for bq24707A is to set the ChargeVoltage() register to 0 V after the battery is fully charged.

8.3.7 Battery Shorted to Ground (BATLOWV)

The IC will disable charge for 1 ms if the battery voltage on SRN falls below 2.5 V. After 1-ms reset, the charge is resumed with soft-start if all the enable conditions in the Enable and Disable Charging sections are satisfied. This prevents any overshoot current in inductor which can saturate inductor and may damage the MOSFET. The charge current is limited to 0.5 A on 10-mΩ current sensing resistor when BATLOWV condition persists and LSFET keeps off. The LSFET turns on only for refreshing pulse to charge BTST capacitor.

8.3.8 Thermal Shutdown Protection (TSHUT)

The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off for self-protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction temperature falls below 135°C. During thermal shutdown, the REGN LDO current limit is reduced to 16 mA. Once the temperature falls below 135°C, charge can be resumed with soft-start.

8.4.1 Enable and Disable Charging

In Charge mode, the following conditions have to be valid to start charge:

• Charge is enabled through SMBus (ChargeOption() bit [0] = 0, default is 0, charge enabled).
• ILIM pin voltage higher than 105 mV.
• All three regulation limit DACs have a valid value programmed.
• ACOK is valid (see Adapter Detect and ACOK Output for details).
• V_SRN does not exceed BATOVP threshold.
• IC temperature does not exceed TSHUT threshold.
• Not in ACOC condition (see Input Overcurrent Protection (ACOC) for details).

One of the following conditions stops ongoing charging:

• Charge is inhibited through SMBus (ChargeOption() bit[0] = 1).
• ILIM pin voltage lower than 75 mV.
• One of three regulation limit DACs is set to 0 or out of range.
• ACOK is pulled high (see Adapter Detect and ACOK Output for details).
• V_SRN exceeds BATOVP threshold.
• TSHUT IC temperature threshold is reached.
• ACOC is detected (see Input Overcurrent Protection (ACOC) for details).
• Short-circuit is detected (see Inductor Short, MOSFET Short Protection for details).
• Watchdog timer expires if watchdog timer is enabled (see Charge Timeout for details).

8.4.2 Continuous Conduction Mode (CCM)

With sufficient charge current the IC inductor current never crosses zero, which is defined as continuous conduction mode. The controller starts a new cycle with ramp coming up from 200 mV. As long as EAO voltage is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO voltage, the HSFET turns off and the low-side MOSFET (LSFET) turns on. At the end of the cycle, the ramp gets reset and the LSFET turns off, ready for the next cycle. There is always break-before-make logic during the transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the low-side power MOSFET conducts the inductor current.

During CCM mode, the inductor current is always flowing and creates a fixed two-pole system. Having the LSFET turn on keeps the power dissipation low and allows safely charging at high currents.

8.4.3 Discontinuous Conduction Mode (DCM)

During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to zero, the converter enters Discontinuous Conduction Mode. Every cycle, when the voltage across SRP and SRN falls below 5 mV (0.5 A on 10 mΩ), the undercurrent protection comparator (UCP) turns off LSFET to avoid negative inductor current, which may boost the system through the body diode of HSFET.

During the DCM mode the loop response automatically changes. It changes to a single pole system and the pole is proportional to the load current.

Both CCM and DCM are synchronous operation with LSFET turnon every clock cycle. If the average charge current goes below 125 mA on a 10-mΩ current-sensing resistor or the battery voltage falls below 2.5 V, the LSFET keeps turnoff. The battery charger operates in nonsynchronous mode and the current flows through the LSFET body diode. During nonsynchronous operation, the LSFET turns on only for refreshing pulse to charge BTST capacitor. If the average charge current goes above 250 mA on a 10-mΩ current sensing resistor, the LSFET exits nonsynchronous mode and enters synchronous mode to reduce LSFET power loss.

8.5.1 SMBus Interface

The IC operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The IC uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The IC uses the SMBus Read-Word and Write-Word protocols (see Figure 12) to communicate with the smart battery. The IC performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the IC has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).

SMBus communication is enabled with the following conditions:

• V_VCC is above UVLO.
• V_ACDET is above 0.6 V.

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a START condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 13 and Figure 14 show the timing diagrams for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the IC because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The IC supports the charger commands as described in Table 2.

Figure 12. SMBus Write-Word and Read-Word Protocols

Figure 13. SMBus Write Timing

Figure 14. SMBus Read Timing

8.5.2 Battery-Charger Commands

The IC supports six battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the IC. The ManufacturerID() command always returns 0x0040H and the DeviceID() command always returns 0x000AH.

8.5.3 Setting Charger Options

By writing ChargeOption() command (0x12H or 0b00010010), the IC allows users to change several charger options after POR (Power On Reset) as shown in Table 3.

8.5.4 Setting the Charge Current

To set the charge current, write a 16-bit ChargeCurrent() command (0x14H or 0b00010100) using the data format listed in Table 4. With a 10-mΩ sense resistor, the IC provides a charge current range of 128 mA to 8.128 A, with 64-mA step resolution. Sending ChargeCurrent() below 128 mA or above 8.128 A clears the register and terminates charging. Upon POR, charge current is 0 A. A 0.1-µF capacitor between SRP and SRN for differential mode filtering, a 0.1-µF capacitor between SRN and ground for common-mode filtering, and an optional 0.1-µF capacitor between SRP and ground for common-mode filtering is recommended. Meanwhile, the capacitance on SRP should not be higher than 0.1 µF to properly sense the voltage across SRP and SRN for cycle-by-cycle undercurrent and overcurrent detection.

The SRP and SRN pins are used to sense R_SR with a default value of 10 mΩ. However, resistors of other values can also be used. With a larger sense resistor comes a larger sense voltage and higher regulation accuracy, but at the expense of higher conduction loss. If the current sensing resistor value is too high, it may trigger overcurrent protection threshold due to the current ripple voltage being too high. In such a case, either a higher inductance value or a lower current-sensing resistor value should be used to limit the current ripple voltage level. TI recommends a current-sensing resistor value of no more than 20 mΩ

To provide secondary protection, the IC has an ILIM pin with which the user can program the maximum allowed charge current. Internal charge current limit is the lower one between the voltage set by ChargeCurrent(), and voltage on the ILIM pin. To disable this function, the user can pull ILIM above 1.6 V, which is the maximum charge current regulation limit. The following equation shows the voltage should add on the ILIM pin with respect to the preferred charge current limit:

Equation 1.

8.5.5 Setting the Charge Voltage

To set the output charge regulation voltage, write a 16bit ChargeVoltage() command (0x15H or 0b00010101) using the data format listed inTable 5. The IC provides a charge voltage range from 1.024 V to 19.200 V, with a 16-mV step resolution. Sending ChargeVoltage() below 1.024 V or above 19.2 V clears the register and terminates charging. Upon POR, the charge voltage limit is 0 V.

The SRN pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, and directly place a decoupling capacitor (0.1 µF recommended) as close to the IC as possible to decouple high frequency noise.

8.5.6 Setting Input Current

System current normally fluctuates as portions of the system are powered up or put to sleep. With the input current limit, the output current requirement of the AC wall adapter can be lowered, reducing system cost.

The total input current, from a wall cube or other DC source, is the sum of the system supply current and the current required by the charger. When the input current exceeds the set input current limit, the IC decreases the charge current to provide priority to system load current. As the system current rises, the available charge current drops linearly to zero. Thereafter, all input current goes to system load and input current increases.

During DPM regulation, the total input current is the sum of the device supply current I_BIAS, the charger input current, and the system load current I_LOAD, and can be estimated as follows:

Equation 2.

where

• η is the efficiency of the charger buck converter (typically 85% to 95%).

To set the input current limit, write a 16-bit InputCurrent() command (0x3FH or 0b00111111) using the data format listed in Table 6. When using a 10-mΩ sense resistor, the IC provides an input-current limit range of 128 mA to 8.064 A, with 128-mA resolution. An input current limit set to no less than 512 mA is suggested. Sending InputCurrent() below 128 mA or above 8.064 A clears the register and terminates charging. Upon POR, the default input current limit is 4096 mA.

The ACP and ACN pins are used to sense R_AC with a default value of 10 mΩ. However, resistors of other values can also be used. With a larger sense resistor, comes a larger sense voltage, and a higher regulation accuracy; but, at the expense of higher conduction loss.

Instead of using the internal DPM loop, the user can build up an external input current regulation loop and have the feedback signal on ILIM. To disable the internal DPM loop, set the input current limit register value to a maximum 8.064 A or a value much higher than the external DPM set point.

If input current rises above 108% of the input current limit set point, the charger shuts down immediately to let the input current fall fast. After stopping charge, the charger soft restarts to charge the battery if the adapter still has power left to charge the battery. This prevents overloading the adapter to crash when system has a high and fast loading transient. The wait time between shutdown and restart charging is a natural response time of the input current limit loop.

8.5.7 Adapter Detect and ACOK Output

The IC uses an ACOK comparator to determine the source of power on the VCC pin, either from the battery or adapter. An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage but lower than the maximum allowed adapter voltage.

The open-drain ACOK output requires an external pullup resistor to the system digital rail for a high level. It can be pulled to ground under the following conditions:

• V_VCC > UVLO.
• 2.4 V < V_ACDET (not in low input voltage condition).
• V_VCC–V_SRN > 245 mV (not in sleep mode).

The default delay is 1.3 s for bq24707 and 1.2 ms for bq24707A after ACDET has valid voltage to make ACOK pull low. The delay can be reduced by a SMBus command (ChargeOption() bit[15] = 0 ACOK delay 1.3 s for bq24707 and 1.2 ms for bq24707A, bit[15] = 1 ACOK no delay). To change this option, the VCC pin voltage must be above UVLO and the ACDET pin voltage must be above 0.6 V to enable IC SMBus communication and set ChargeOption() bit[15] to 1 to disable the ACOK deglitch timer.

8.5.8 Converter Operation

The synchronous buck PWM converter uses a fixed-frequency voltage mode control scheme and internal type III compensation network. The LC output filter generates the following characteristic resonant frequency:

Equation 3.

The resonant frequency f_o is used to determine the compensation to ensure there is sufficient phase margin and gain margin for the target bandwidth. The LC output filter should be selected to generate a resonant frequency of 10–20 kHz nominal for the best performance. The suggested component values per charge current with a 750-kHz default switching frequency is shown in Table 7.

Ceramic capacitors show a DC-bias effect. This effect reduces the effective capacitance when a DC-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a DC-bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value to get the required value at the operating point.

The IC has three loops of regulation: input current, charge current, and charge voltage. The three loops are brought together internally at the error amplifier. The maximum voltage of the three loops appears at the output of the error amplifier EAO (see ). An internal saw-tooth ramp is compared to the internal error control signal EAO to vary the duty-cycle of the converter. The ramp has an offset of 200 mV to allow 0% duty-cycle.

When the battery charge voltage approaches the input voltage, the EAO signal is allowed to exceed the saw-tooth ramp peak to get a 100% duty-cycle. If voltage across the BTST and PHASE pins falls below 4.3 V, a refresh cycle starts and the low-side N-channel power MOSFET is turned on to recharge the BTST capacitor. It can achieve a duty-cycle of up to 99.5%.

8.5.9 EMI Switching Frequency Adjust

The charger switching frequency can be adjusted ±18% to solve EMI issue through SMBus command. ChargeOption() bit [9]=0 disable the frequency adjust function. To enable frequency adjust function, set ChargeOption() bit[9]=1. Set ChargeOption() bit [10]=0 to reduce switching frequency, set bit[10]=1 to increase switching frequency.

If frequency is reduced, for a fixed inductor the current ripple is increased. Inductor value must be carefully selected so that it will not trigger cycle-by-cycle peak overcurrent protection even for the worst condition such as higher input voltage, 50% duty cycle, lower inductance and lower switching frequency.

8.5.10 Inductor Short, MOSFET Short Protection

The IC has a unique short-circuit protection feature. The cycle-by-cycle current monitoring feature of the IC is achieved through monitoring the voltage drop across R_DS(on) of the MOSFETs after a certain amount of blanking time. In case of MOSFET short or inductor short circuit, the overcurrent condition is sensed by two comparators and two counters will be triggered. After seven times of short circuit events, the charger will be latched off. To reset the charger from latch-off status, the IC VCC pin must be pulled down below UVLO or ACDET pin must be pulled down below 0.6 V. This can be achieved by removing the adapter and shut down the operation system. The low-side MOSFET short circuit voltage drop threshold is fixed to typical 110 mV. The high-side MOSFET short-circuit voltage drop threshold can be adjusted through SMBus command. ChargeOption() bit[8:7] = 00, 01, 10, 11 set the threshold 300 mV, 500 mV, 700 mV, and 900 mV, respectively.

Due to the certain amount of blanking time to prevent noise when MOSFET just turns on, the cycle-by-cycle charge overcurrent protection may detect high current and turn off MOSFET first before the short-circuit protection circuit can detect short condition because the blanking time has not finished. In such a case, the charge may not be able to detect shorts circuit and counter may not be able to count to seven then latch off. Instead, the charge may continuously keep switching with very narrow duty cycle to limit the cycle-by-cycle current peak value. However, the charger should still be safe and will not cause failure because the duty cycle is limited to a very short of time and MOSFET should be still inside the safety operation area. During a soft-start period, it may take a long time instead of just seven switching cycles to detect short circuit based on the same blanking time reason.

8.5.11 Independent Comparator

The IC has an independent comparator can be used to compare input current, charge current, or battery voltage with internal reference . Program CMPIN voltage by connecting a resistor-divider from IOUT pin to CMPIN pin to GND pin for adapter or charge current comparison or from SRN pin to CMPIN pin to GND pin for battery voltage comparison. When CMPIN is above internal reference, CMPOUT is pulled to external pullup rail by external pullup resistor. When CMPIN is below internal reference, CMPOUT is pulled to GND by internal MOSFET. Place a resistor between CMPIN and CMPOUT to program hysteresis. The internal reference can be set to 0.6 V or 2.4 V through SMBus command (ChargeOption() bit[4]=0 set internal reference 0.6 V, bit[4]=1 set 2.4 V).

There is one 50-kΩ series resistor R_S and one 2000-kΩ pulldown resistor R_DOWN for CMPIN pin as shown in Figure 15. To get the accurate comparison set point, these two resistors must be included in the calculation. A spreadsheet calculation tool has been developed to simplify the design work. User can download from the TI Web site at www.ti.com under the IC product folder.

Figure 15 also shows one application circuit using this comparator for battery voltage comparison. After using the superposition principle and fill the components value into the spreadsheet the battery voltage threshold is 9.45 V for rising edge and 8.99 V for falling edge.

Figure 15. IC Comparator Internal Circuit and Application Circuit