8.3.1 Battery Only

Battery is connected to VCC via diode. When VCC voltage is above UVLO, bq2477x powers up to turn on BATFET and starts SMBus/I2C communication. By default, bq2477x stays in low power mode (0x12[15] = 1) with lowest quiescent current.

When 0x12[15] is set to 0, the device enters performance mode. The user can enable IBAT buffer through SMBus/I2C. In order to enable PMON, PROCHOT or independent comparator, the bq2477x enables REGN LDO for accurate reference.

8.3.2 Adapter Detect and ACOK Output

An external resistor divider attenuates the adapter voltage before it goes to ACDET. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage, but lower than the maximum allowed adapter voltage. When ACDET is above 0.6V, REGN LDO and bias circuits are enabled.

The open drain ACOK output can be pulled to external rail under the following conditions:

• V_(UVLO) < V_(VCC) < V_(ACOVP)
• V_(ACDET) > 2.4 V
• V_(VCC) – V_(SRN) > V_{(VCC_SRN_RISE)}

8.3.3 System Power Selection

The bq2477x device automatically switches adapter or battery power to system.

The ACDRV drives a pair of common-source (CMSRC) N-channel power MOSFETs (ACFET and RBFET) between adapter and ACP (see Figure 21 for details). The ACFET separates adapter from system and battery, and provides a limited di/dt when plugging in adapter by controlling the ACFET turn-on time. The RBFET provides negative input voltage protection and battery discharge protection when adapter is shorted to ground, and minimizes system power dissipation with its low R_DS(on) compared to a Schottky diode.

When the adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off, disconnecting the adapter from the system. BATDRV stays as low as VSRN – 10 V to connect battery to system if all of the following conditions are valid:

• V_(VCC) > V_(UVLO)
• V_(SRN) – V_(SRP) > 2.56 mV

After the adapter plugs in, the system power source switches from battery to adapter if ACOK is HIGH. The gate drive voltage on ACFET and RBFET is V_(CMSRC) + 6 V. If ACDRV-CMSRC voltage drops at least 100 mV from its normal voltage, the converter stops.

To limit the adapter inrush current during ACFET turn-on, the Cgs and Cgd external capacitor of ACFET must be carefully selected following the guidelines below:

• Minimize total capacitance on system
• Cgs should be 40× or higher than Cgd to avoid ACFET false turn on during adapter hot plug-in
• Check with MOSFET vendor on peak current rating
• Place 4 kΩ resistor in series with ACDRV and CMSRC pins to limit MOSFET turn on/off time.

8.3.4 System Power Up

After the ACFET is turned on, the converter is enabled and the HSFET and LSFET start switching. Every time the buck converter is started, the IC automatically applies soft-start (no soft-start when exit LEARN) on buck output current to avoid any overshoot or stress on the output capacitors or the power converter. No external components are needed for this function.

When power up, the converter output voltage is a default value set by CELL pin configuration.

8.3.5 Current and Power Monitor

8.3.6 Processor Hot Indication for CPU Throttling

When CPU is running turbo mode, the peak power may exceed total available power from adapter and battery. The adapter current and battery discharge overshoot, or system voltage drop indicates the system power may be too high. When the adapter or battery is removed, the remaining power source may not support the peak power in turbo mode. The processor hot function in bq2477x monitors these events, and PROCHOT pulse is asserted.

The PROCHOT triggering events include:

• ICRIT: adapter peak current
• INOM: adapter average current (110% of input current limit)
• IDCHG: battery discharge current
• VSYS: system voltage on SRN for 2s - 4s battery
• ACOK: upon adapter removal (ACOK pin HIGH to LOW)
• BATPRES: upon battery removal (BATPRES pin LOW to HIGH)
• CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)

The threshold of ICRIT, IDCHG or VSYS, and the deglitch time of ICRIT, INOM, IDCHG or CMPOUT are programmable through SMBus. Each triggering event can be individually enabled in REG0x3D[6:0].

Figure 5. PROCHOT Profile

When any event in PROCHOT profile is triggered, PROCHOT is asserted low for minimum 10 ms (default 0x3C[4:3]). At the end of the 10 ms, if the PROCHOT event is still active, the pulse gets extended.

8.3.7 Converter Operation

The bq2477x typically use 2.2/3.3 µH inductor and 60 µF output capacitance to achieve all loops stable. This capacitance could be from system bus decoupling cap. But in order to achieve good output transient response, like mini output drop or min output spike, then it is better to have more output capacitance from the system bus, which could be the total input capacitance from the input of the down-stream DC-DC converters for CPU core, DDR and chip-set.

Ceramic capacitors show a DC-bias effect. This effect reduces the effective capacitance when a DC-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a DC bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value to get the required value at the operating point.

8.3.8 Learn Mode

LEARN mode is set up to calibrate gauge in the pack. When LEARN is enabled, the system first discharge the battery below depletion threshold, and complete another charging cycle for gauge calibration. During the discharging, BATFET turns on and converter stops.

A battery LEARN cycle can be activated via SMBus/I2C "LEARN Enable" command (ChargeOption0() bit[5]=1 enable Learn Mode). When LEARN is enabled with an adapter connected, the system power switch to battery by turning off converter and keep ACFET/BATFET on. Learn mode allows the battery to discharge in order to calibrate the battery gas gauge over a complete discharge/charge cycle. When LEARN is disabled, the system power switch to adapter by turning on converter in a few hundreds μs.

bq2477x also supports hardware pin to exist LEARN mode by driving BATPRES to HIGH. When BATPRES pin is pulled to HIGH, bq2477x resets "LEARN Enable" (ChargeOption0() bit[5]) and IDPM_EN (ChargeOption() bit[1]), and reset MaxChargeVoltage() and ChargeCurrent().

8.3.9 Charger Timeout

The bq2477x includes a watchdog timer to terminate charging if the charger does not receive a write MaxChargeVoltage() or write ChargeCurrent() command within 175s (adjustable via ChargeOption() command). If a watchdog timeout occurs all register values keep unchanged but charge is suspended. Write ChargeVoltage() or write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. The watchdog timer can be disabled, or set to 44s, 88s or 175s via SMBus command (ChargeOption() bit[14:13]). If watchdog is in timeout, disabling watchdog timer by writing ChargeOption() bit[14:13] also resumes charging.

8.3.10 Device Protection Features

8.4.1 Battery Charging

The bq2477x charges 1-4 cell battery in constant current (CC), and constant voltage (CV) mode. The host programs battery voltage to ChargeVoltage() (0x15()). According to battery voltage, the host programs appropriate charge current to ChargeCurrent() (0x14()). When battery is full or battery is not in good condition to charge, host terminates charge by setting 0x12[0] to 1, or setting ChargeCurrent() to zero.

See the Feature Description section for details on charge enable conditions and register programming.

8.4.2 System Voltage Regulation with Narrow VDC Architecture

The bq2477x deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by MinSystemVoltage(). Even with a deeply depleted battery, the system is regulated above the minimum system voltage.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode). As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET.

See the Feature Description section for details on system voltage regulation and register programming.

8.5.1 SMBus Interface

The bq24770 device operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The bq24770 device uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24770 device uses the SMBus read-word and write-word protocols (shown in Table 2 and Table 3) to communicate with the smart battery. The bq24770 device performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the bq24770 device has two identification registers, a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).

SMBus/I2C communication starts when VCC is above V_(UVLO).

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a start condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a stop condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 6 and Figure 7 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq2477x device because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq2477x supports the charger commands listed in Table 2.

8.5.1.2 Timing Diagrams

A = Start condition	H = LSB of data clocked into slave
B = MSB of address clocked into slave	I = Slave pulls SMBDATA line low
C = LSB of address clocked into slave	J = Acknowledge clocked into master
D = R/W bit clocked into slave	K = Acknowledge clock pulse
E = Slave pulls SMBDATA line low	L = Stop condition, data executed by slave
F = ACKNOWLEDGE bit clocked into master	M = New start condition
G = MSB of data clocked into slave

Figure 6. SMBus Write Timing

A = Start condition	G = MSB of data clocked into master
B = MSB of address clocked into slave	H = LSB of data clocked into master
C = LSB of address clocked into slave	I = Acknowledge clock pulse
D = R/W bit clocked into slave	J = Stop condition
E = Slave pulls SMBDATA line low	K = New start condition
F = ACKNOWLEDGE bit clocked into master

Figure 7. SMBus Read Timing

8.5.2 I²C Serial Interface

The bq24773 uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I²C is a bi-directional 2-wire serial interface. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address D4H, receiving control inputs from the master device like micro controller or a digital signal processor through REG00-REG0F. The I²C interface supports both standard mode (up to 100kbits), and fast mode (up to 400kbits). connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.

8.5.2.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

Figure 8. Bit Transfer on the I²C Bus

8.5.2.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition.

Figure 9. START and STOP Conditions

8.5.2.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

Figure 10. Data Transfer on the I²C Bus

8.5.2.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

Figure 11. Complete Data Transfer

8.5.2.6 Single Read and Write

Figure 12. Single Write

Figure 13. Single Read

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

8.5.2.7 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write.

Figure 14. Multi Write

Figure 15. Multi Read

Table 4. Battery Charger Command Summary

8.6.1 ChargeOption0 Register

8.6.2 ChargeOption1 Register

8.6.3 ChargeOption2 Register

8.6.4 ProchotOption0 Register

8.6.5 ProchotOption1 Register

8.6.6 Setting the Charge Current

To set the charge current, write a 16-bit ChargeCurrent() command. With 10mΩ sense resistor, the bq2477x provides charge current range of 128mA to 8.128A, with 64mA step resolution. It is suggested to write battery voltage to MaxChargeVoltage() before programming ChargeCurrent(). When battery is absent, the host should write 0A to ChargeCurrent().

During pre-charge, the charge current is clamped at 384mA. Sending ChargeCurrent() 0mA will terminate charge. Upon POR, charge current setting is 0mA.

For 1s charging, the charge current is clamped at 384 mA when battery is below BATLOWV threshold. When battery is between BATLOWV and SYSMIN, the charging current is clamped at 2 A. When battery is above SYSMIN, the charging current follows register setting.

To program charge current in bq24773, the host has to write 2-byte command with REG0A first, followed by REG0B. No other command can be inserted in between. After the completion of REG0A and REG0B, charge current will be updated. If host writes REG0B first, the command will be ignored. If the time between write of REG0A and REG0B exceeds watchdog timer, the REG0A command will be ignored.

The SRP and SRN pins are used to sense voltage drop across R_SR with default value of 10mΩ. For a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy; but at the expense of higher conduction loss. A current sensing resistor value no more than 20mΩ is suggested.

A 0.1µF capacitor between SRP and SRN for differential mode filtering is recommended; a 0.1µF capacitor between SRN and ground, and an optional 0.1µF capacitor between SRP and ground for common mode filtering. Meanwhile, the capacitance on SRP should not be higher than 0.1µF in order to properly sense voltage across SRP and SRN.

8.6.7 Setting the Maximum Charge Voltage

To set the output charge regulation voltage, write a 16-bit MaxChargeVoltage() command. The bq2477x provides charge voltage range from 1.024V to 19.200V, with 16mV step resolution. Upon POR or when charge is disabled, the system is regulated at MaxChargeVoltage().

If enable charge without writing any command to MaxChargeVoltage(), the MaxChargeVoltage() is automatically changed to 4.2V/cell. If disable charge without writing any command to MaxChargeVoltage(), the MaxChargeVoltage() automatically goes back to POR value. Once writing a valid value to MaxChargeVoltage(), the register doesn’t automatically change between charge enable and disable.

The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery pack positive side as possible. A decoupling capacitor of 0.1µF is recommended as close to IC as possible to decouple high frequency noise.

To program charge voltage in bq24773, the host has to write 2-byte command with REG0C first, followed by REG0D. No other command can be inserted in between. After the completion of REG0C and REG0D, charge voltage will be updated. If host writes REG0D first, the command will be ignored. If the time between write of REG0C and REG0D exceeds watchdog timer, the REG0C command will be ignored.

8.6.8 Setting the Minimum Charge Voltage

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. When charge is enabled, and the battery is below MinSystemVoltage(), the system is regulated at the minimum system voltage setting. When charge is disabled, the system is regulated at MaxChargeVoltage().

To set the minimum system voltage, write a 16-bit MinSystemVoltage() command. The bq2477x provides minimum system voltage range from 1.024V to 19.200V, with 256mV step resolution.

8.6.9 Setting Input Current

Normally, input power source powers system and charges battery. With AC wall adapter output current can be regulated to save system cost.

To set the input current limit, write a 16-bit InputCurrent() command. When using a 10mΩ sense resistor, the bq2477x provides an input-current limit range of 128mA to 8.128A, with 64mA resolution. Upon POR, default input current limit is 3.2A (770) or 2.944A (773).

The ACP and ACN pins are used to sense R_(AC) with default value of 10mΩ. However, resistors of other values can also be used. For a larger sense resistor, larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss.