7.3.1 Hall Comparators

Three comparators are provided to process the raw signals from Hall effect transducers to commutate the motor. The Hall amplifiers sense zero crossings of the differential inputs and pass the information to digital logic.

The Hall amplifiers have hysteresis, and their detect threshold is centered at 0. Note, hysteresis is defined as shown in Figure 3:

Figure 3. Hall Amplifier Hysteresis

In addition to hysteresis, the Hall inputs are deglitched with a circuit that ignores any extra Hall transitions for a period of 20 μs after sensing a valid transition. This prevents PWM noise from being coupled into the Hall inputs, which can result in erroneous commutation.

If excessive noise is still coupled into the Hall comparator inputs, it may be necessary to add capacitors between the + and – inputs of the Hall comparators, and (or) between the input or inputs and ground.

The ESD protection circuitry on the Hall inputs implements a diode to VREG. Because of this diode, the voltage on the Hall inputs should not exceed the VREG voltage.

Since VREG is disabled in standby mode (ENABLEn inactive), the Hall inputs should not be driven by external voltages in standby mode. The DRV8307 device specifies if the Hall sensors are powered from VREG or VSW; however, if the Hall sensors are powered externally, they should be disabled when the DRV8307 is put into standby mode. In addition, the Hall sensors should be powered-up before enabling the motor, or an invalid Hall state may cause a delay in motor operation.

7.3.2 HALLOUT Output

The HALLOUT terminal indicates the speed of the motor. It follows the transitions observed from the HALL U hall sensor. Figure 4 shows the HALLOUT signal.

Figure 4. HALLOUT Relationship to Hall Transitions

7.3.3 Enable, Reset, and Clock Generation

The ENABLEn terminal is used to start and stop motor operation. The ENABLEn terminal is active low.

When ENABLEn is active, operation of the motor is enabled. When ENABLEn is made inactive, the motor coasts. After motor rotation has stopped (when no transitions occur on the HALLOUT terminal for a period of 1 s), the DRV8307 device enters a low-power standby state.

When in the standby state:

• The motor driver circuitry is disabled (all gate drive outputs are driven low, so the FET outputs are high-impedance).
• The gate drive regulator and charge pump are disabled.
• The VREG regulator and VSW power switch are disabled.
• All analog circuitry is placed into a low power state.
• The digital circuitry in the device still operates.

All internal logic is reset in two different ways:

• Upon device power-up
• When VM drops below V_RESET

An internal clock generator provides all timing for the DRV8307 device. The master oscillator runs at 100 MHz. This clock is divided to a nominal 50-MHz frequency that clocks the remainder of the digital logic.

7.3.4 Commutation

For 3-phase brushless DC motors, rotor position feedback is provided from Hall effect transducers mounted on the motor. These transducers provide three overlapping signals, each 60° apart. The windings are energized in accordance with the signals from the Hall sensors to cause the motor to move.

In addition to the Hall sensor inputs, commutation is affected by a direction control, which alters the direction of motion by reversing the commutation sequence. Control of commutation direction is by the DIR input terminal.

If the commanded direction changes while the motor is moving, the device allows the motor to coast until the motor stops. The stopped condition is determined by measuring the period of the HALL_U signal; when the period exceeds 160 ms, typical operation resumes and the motor starts spinning in the commanded direction. This prevents excessive current flow in the output stage if the motor is reversed while running at speed.

In standard 120° commutation, mis-positioning the Hall sensors can cause motor noise, vibration, and torque ripple. 120° commutation using a single Hall sensor (single-Hall commutation) can improve motor torque ripple and vibration because it relies on only one Hall edge for timing.

7.3.4.1 120° 3-Hall Commutation

In standard 120° commutation, the motor phases are energized using simple combination logic based on all three Hall sensor inputs.

Standard 120° commutation is in accordance with Table 1, Figure 5, and Figure 6:

Table 1. Standard 120° Commutation⁽¹⁾

STATE	HALL INPUTS						PRE-DRIVE OUTPUTS
	DIR = 1			DIR = 0			Phase U		Phase V		Phase W
	U_H	V_H	W_H	U_H	V_H	W_H	U_HSGATE	U_LSGATE	V_HSGATE	V_LSGATE	W_HSGATE	W_LSGATE
1	L	L	H	H	H	L	L	L	PWM	L / !PWM(2)	L	H
2	L	H	H	H	L	L	PWM	L / !PWM(2)	L	L	L	H
3	L	H	L	H	L	H	PWM	L / !PWM(2)	L	H	L	L
4	H	H	L	L	L	H	L	L	L	H	PWM	L / !PWM(2)
5	H	L	L	L	H	H	L	H	L	L	PWM	L / !PWM(2)
6	H	L	H	L	H	L	L	H	PWM	L / !PWM(2)	L	L
1X	H	H	H	L	L	L	L	L	L	L	L	L
2X	L	L	L	H	H	H	L	L	L	L	L	L

(1) Hall sensor is H if the positive input terminal voltage is higher than the negative input terminal voltage. States 1X and 2X are illegal input combinations.

(2) During states where the phase is driven with a PWM signal, using asynchronous rectification, the LS gate is held off (L); using synchronous rectification, the LS gate is driven with the inverse of the HS gate.

(1) !PWM for Sync Rectification

Figure 5. Standard 120° Commutation (DIR = 1)

Figure 6. Standard 120° Commutation (DIR = 0)

7.3.5 Braking

Motor braking can be initiated by the BRAKE terminal.

When the motor is braking, all low-side drivers are held in an on state, causing all low-side FETs to turn on.

7.3.6 Output Pre-Drivers

The output drivers for each phase consist of N-channel and P-channel MOSFET devices arranged as a CMOS buffer. They are designed to directly drive the gate of external N-channel power MOSFETs. The outputs provide synchronous rectification operation. In synchronous rectification, the low-side FET is turned on when the high side is turned off.

The high-side gate drive output UHSG is driven to VCP whenever the duty cycle output U_PD from the PWM generator is high, the enable signal U_HS from the commutation logic is active, and the current limit (V_LIMITER) is not active. If the high-side FET is on and a current limit event occurs, the high-side FET is immediately turned off until the next PWM cycle.

The low-side gate drive ULSG is driven to V_OUTL whenever the internal signal U_LS is high, or whenever synchronous rectification is active and UHSG is low.

Phases V and W operate in an identical fashion.

Figure 7. Pre-Driver Block Diagram

Figure 8. Gate Control Behavior

The peak drive current of the pre-drivers is fixed at 30 mA.

When changing the state of the output, the peak current is applied for a short period of time (15 μs) to charge the gate capacitance. After this time, a weak current source is used to keep the gate at the desired state.

During high-side turn-on, the low-side gate is held low with a low impedance. This prevents the gate-source capacitance of the low-side FET from inducing turn-on. Similarly, during low-side turn-on, the high-side gate is held off with a low impedance.

The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and low-side FETs from conducting at the same time.

7.3.7 Current Limit

The current limit circuit activates if the voltage detected across the low-side sense resistor exceeds V_LIMITER. Note that the current limit circuit is ignored immediately after the PWM signal goes active for a short blanking time, to prevent false trips of the current limit circuit.

If current limit activates, the high-side FET is disabled until the beginning of the next PWM cycle. If synchronous rectification is enabled when the current limit activates, the low-side FET is activated while the high-side FET is disabled.

7.3.8 Charge Pump

Since the output stages use N-channel FETs, a gate drive voltage higher than the VM power supply is needed to fully enhance the high-side FETs. The DRV8307 device integrates a charge pump circuit that generates a voltage approximately 10 V more than the VM supply for this purpose.

The charge pump requires two external capacitors for operation. For details on these capacitors (value, connection, and so forth), refer to Figure 9.

The charge pump is shut down when in standby mode (ENABLEn inactive).

Figure 9. Charge Pump Block Diagram

7.3.9 5-V Linear Regulator

A 5-V linear regulator (VREG) is provided to power internal logic and external circuitry, such as the Hall effect sensors.

A capacitor must be connected from the VREG output to ground, even if the output is not used for external circuitry. The recommended capacitor value is a 0.1-μF, 10-V ceramic capacitor.

The VREG output is designed to provide up to 30-mA output current, but power dissipation and thermal conditions must be considered. As an example, with 24 V in and 20 mA out, power dissipated in the linear regulator is 19 V × 20 mA = 380 mW.

The VREG regulator is shutdown in standby mode (when ENABLEn is inactive).

7.3.10 Power Switch

A low-current switch is provided in the DRV8307 device that can be used to power the Hall sensors or other external circuitry through the VSW terminal. When ENABLEn is active the switch is turned on, connecting the VSW terminal to VM. When ENABLEn is inactive the switch is turned off (standby mode).

7.3.11 Protection Circuits

A number of protection circuits are included in the DRV8307 device. Faults are reported by asserting the FAULTn terminal (an active-low, open-drain output signal).

7.4.1 Clock PWM Mode

In PWM input mode, the PWM input signal is timed using a 50-MHz clock to generate a 12-bit number that corresponds to the duty cycle of the incoming PWM signal. The input PWM frequency should be between 16 and 50 kHz; higher PWM frequencies work, but resolution is degraded. Note that the gate driver’s output PWM frequency is independent of the speed control PWM input frequency; the output PWM frequency is 25 kHz.

The outputs of the PWM generators are the signals U_PD, V_PD, and W_PD. These contain the duty cycle information for each phase.

Figure 10 shows modulation and PWM generation.

Figure 10. Modulation and PWM Generation

When the DRV8307 is driving a motor, the motor should not be stopped by setting the PWM input to 0% duty cycle. Instead, ENABLEn should be brought high.