9.3.1.1 Background Calibration

Background calibration is the process of continuously determining and applying the offset and gain calibration coefficients to the output codes to minimize the LMP900xx’s offset and gain errors. Background calibration is a feature built into the LMP900xx and is automatically done by the hardware without interrupting the input signal.

Four differential channels, CH0-CH3, each with its own gain and ODRs, can be calibrated to improve the accuracy.

9.3.1.1.2 Using Background Calibration:

There are four modes of background calibration, which can be programmed using the BGCALCN bits. They are as follows:

• BgcalMode0: Background Calibration OFF
• BgcalMode1: Offset Correction / Gain Estimation
• BgcalMode2: Offset Correction / Gain Correction. Follow Figure 40 to set other appropriate registers when using this mode.
• BgcalMode3: Offset Estimation / Gain Estimation

 

Figure 40. BgcalMode2 Register Settings

If operating in BgcalMode2, four channels (with the same ODR) are being converted, and FGA_BGCAL = 0 (default), then the ODR is reduced by:

1. 0.19% of 1.6775 SPS
2. 0.39% of 3.355 SPS
3. 0.78% of 6.71 SPS
4. 1.54% of 13.42 SPS
5. 3.03% of 26.83125 SPS
6. 5.88% of 53.6625 SPS
7. 11.11% of 107.325 SPS
8. 20% of 214.65 SPS

9.3.1.2 System Calibration

The LMP900xx provides some unique features to support easy system offset and system gain calibrations.

The System Calibration Offset Registers (CHx_SCAL_OFFSET) hold the System Calibration Offset Coefficients in 16-bit, two's complement binary format. The System Calibration Gain Registers (CHx_SCAL_GAIN) hold the System Calibration Gain Coefficient in 16-bit, 1.15, unsigned, fixed-point binary format. For each channel, the System Calibration Offset coefficient is subtracted from the conversion result prior to the division by the System Calibration Gain coefficient.

A data-flow diagram of these coefficients can be seen in Figure 41.

Figure 41. System Calibration Data-Flow Diagram

There are four distinct sets of System Calibration Offset and System Calibration Gain Registers for use with CH0-CH3. CH4-CH6 reuse the registers of CH0-CH2, respectively.

The LMP900xx provides two system calibration modes that automatically fill the Offset and Gain coefficients for each channel. These modes are the System Calibration Offset Coefficient Determination mode and the System Calibration Gain Coefficient Determination mode. The System Calibration Offset Coefficient Determination mode must be entered prior to the System Calibration Gain Coefficient Determination mode, for each channel.

The system zero-scale condition is a system input condition (sensor loading) for which zero (0x0000) system-calibrated output code is desired. It may not, however, cause a zero input voltage at the input of the ADC.

The system reference-scale condition is usually the system full-scale condition in which the system's input (or sensor's loading) would be full-scale and the desired system-calibrated output code would be 0x8000 (unsigned 16-bit binary). However, system full-scale condition need not cause full-scale input voltage at the input of the ADC.

The system reference-scale condition is not restricted to just the system full-scale condition. In fact, it can be any arbitrary fraction of full-scale (up to 1.25 times) and the desired system-calibrated output code can be any appropriate value (up to 0xA000). The CHx_SCAL_GAIN register must be written with the desired system-calibrated output code (default:0x8000) before entering the System Calibration Gain Coefficient Determination mode. This helps in in-place system calibration.

9.3.1.2.3 Post-Calibration Scaling

LMP900xx allows scaling (multiplication and shifting) for the System Calibrated result. This eases downstream processing, if any. Multiplication is done using the System Calibration Scaling Coefficient in the CHx_SCAL_SCALING register and shifting is done using the System Calibration Bits Selector in the CHx_SCAL_BITS_SELECTOR register.

The System Calibration Bits Selector value should ideally be the logarithm (to the base 2) of the System Calibration Scaling Coefficient value.

There are four distinct sets of System Calibration Scaling and System Calibration Bits Selector Registers for use with CH0-CH3. CH4-CH6 reuse the registers of CH0-CH2, respectively.

A data-flow diagram of these coefficients can be seen in Figure 42.

Figure 42. Post-Calibration Scaling Data-Flow Diagram

9.3.7.1 Reference Input (V_REF)

The differential reference voltage V_REF (V_REFP – V_REFN) sets the range for V_IN.

The muxed V_REF allows the user to choose between V_REF1 or V_REF2 for each channel. This selection can be made by programming the V_{REF_SEL} bit in the CHx_INPUTCN registers (CHx_INPUTCN: V_{REF_SEL}). The default mode is V_REF1. If V_REF2 is used, then V_IN6 and V_IN7 cannot be used as inputs because they share the same pin.

Refer to VREF for V_REF applications information.

9.3.7.2 Flexible Input MUX (VIN)

LMP900xx provides a flexible input MUX as shown in Figure 43. The input that is digitized is V_IN = V_INP – V_INN; where V_INP and V_INN can be any available input.

The digitized input is also known as a channel, where CH = V_IN = V_INP – V_INN. Thus, there are a maximum of 4 differential channels: CH0, CH1, CH2, and CH3 for the LMP90080/LMP90079. The LMP90078/LMP90077 has 2 differential channels: CH0 and CH1 because it does not have the V_IN3, V_IN4, and V_IN5 pins.

LMP900xx can also be configured single-ended, where the common ground is any one of the inputs. There are a maximum of 7 single-ended channels: CH0, CH1, CH2, CH3, CH4, CH5, and CH6 for the LMP90080/LMP90079 and 4: CH0, CH1, CH2, CH3 for the LMP90078/LMP90077.

The input MUX can be programmed in the CHx_INPUTCN registers. For example on the LMP90080, to program CH0 = V_IN = V_IN4 – V_IN1, go to the CH0_INPUTCN register and set:

1. V_INP = 0x4

2. V_INN = 0x1

Figure 43. Simplified VIN Circuitry

9.3.7.3 Selectable Gains (FGA and PGA)

LMP900xx provides two types of gain amplifiers: a fixed gain amplifier (FGA) and a programmable gain amplifier (PGA). FGA has a fixed gain of 16x or it can be bypassed, while the PGA has programmable gain settings of 1x, 2x, 4x, or 8x.

Total gain is defined as FGA x PGA. Thus, LMP900xx provides gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x with true continuous background calibration.

The gain is channel specific, which means that one channel can have one gain, while another channel can have the same or a different gain.

The gain can be selected by programming the CHx_CONFIG: GAIN_SEL bits.

9.3.7.4 Buffer (BUFF)

There is an internal unity gain buffer that can be included or excluded from the signal path. Including the buffer provides a high input impedance but increases the power consumption.

When gain ≥ 16, the buffer is automatically included in the signal path. When gain < 16, including or excluding the buffer from the signal path can be done by programming the CHX_CONFIG: BUF_EN bit.

9.3.7.5 Internal/External CLK Selection

LMP900xx allows two clock options: internal CLK or external CLK (crystal (XTAL) or clock source).

There is an “External Clock Detection” mode, which detects the external XTAL if it is connected to XOUT and XIN. When operating in this mode, the LMP900xx shuts off the internal clock to reduce power consumption. Below is a flow chart to help set the appropriate clock registers.

Figure 44. CLK Register Settings

The recommended value for the external CLK is discussed in the next sections.

9.3.7.6 Programmable ODRS

If using the internal CLK or external CLK of 3.5717 MHz, then the output date rates (ODR) can be selected (using the ODR_SEL bit) as:

1. 13.42/8 = 1.6775 SPS

2. 13.42/4 = 3.355 SPS

3. 13.42/2 = 6.71SPS

4. 13.42 SPS

5. 214.65/8 = 26.83125 SPS

6. 214.65/4 = 53.6625 SPS

7. 214.65/2 = 107.325 SPS

8. 214.65 SPS (default)

If the internal CLK is not being used and the external CLK is not 3.5717 MHz, then the ODR will be different. If this is the case, use the equation below to calculate the new ODR values.

For example, a 3.6864 MHz XTAL or external clock has the following ODR values:

The ODR is channel specific, which means that one channel can have one ODR, while another channel can have the same or a different ODR.

Note that these ODRs are meant for a single channel conversion; the ODR needs to be divided by n for n channels scanning. For example, if the ADC were running at 214.65 SPS and four channels are being scanned, then the ODR per channel would be 214.65/4 = 53.6625 SPS.

9.3.7.7 Digital Filter

The LMP900xx has a fourth order rotated sinc filter that is used to configure various ODRs and to reject power supply frequencies of 50Hz and 60Hz. The 50/60 Hz rejection is only effective when the device is operating at ODR ≤ 13.42 SPS. If the internal CLK or the external CLK of 3.5717 MHz is used, then the LMP900xx will have the frequency response shown in Figure 45 through Figure 49.

Figure 45. Digital Filter Response, 1.6775 SPS and 3.355 SPS

Figure 47. Digital Filter Response at 13.42 SPS

Figure 49. Digital Filter Response 107.325 SPS and 214.65 SPS

Figure 46. Digital Filter Response, 6.71 SPS and 13.42 SPS

Figure 48. Digital Filter Response, 26.83125 SPS and 53.6625 SPS

Figure 50. Digital Filter Response for a 3.5717 MHz Versus 3.6864 MHz XTAL

If the internal CLK is not being used and the external CLK is not 3.5717 MHz, then the filter response would be the same as the response shown above, but the frequency will change according to the equation:

Using Equation 9, an example of the filter response for a 3.5717 MHz XTAL versus a 3.6864 MHz XTAL can be seen in Figure 50.

9.3.7.8 GPIO (D0–D6)

Pins D0-D6 are general purpose input/output (GPIO) pins that can be used to control external LEDs or switches. Only a high or low value can be sourced to or read from each pin.

Figure 51 shows a flowchart how these GPIOs can be programmed.

Figure 51. GPIO Register Settings

9.4.1.1 ScanMode0: Single-Channel Continuous Conversion

LMP900xx continuously converts the selected FIRST_CH.

Do not operate in this scan mode if gain ≥ 16 and the LMP900xx is running in background calibration modes BgcalMode1 or BgcalMode2. If this is the case, then it is more suitable to operate the device in ScanMode2 instead.

9.4.1.2 ScanMode1: Multiple-Channels Single Scan

LMP900xx converts one or more channels starting from FIRST_CH to LAST_CH, and then enters the stand-by state.

9.4.1.3 ScanMode2: Multiple-Channels Continuous Scan

LMP900xx continuously converts one or more channels starting from FIRST_CH to LAST_CH, and then it repeats this process.

9.4.1.4 ScanMode3: Multiple-Channels Continuous Scan with Burnout Currents

This mode is the same as ScanMode2 except that the burnout current is provided in a serially scanned fashion (injected in a channel after it has undergone a conversion). Thus it avoids burnout current injection from interfering with the conversion result for the channel.

The sensor diagnostic burnout currents are available for all four scan modes. The burnout current is further gated by the BURNOUT_EN bit for each channel. ScanMode3 is the only mode that scans multiple channels while injecting burnout currents without interfering with the signal. This is described in details in Burnout Currents.

9.4.2.1 IB1 & IB2 - Excitation Currents (LMP90080/LMP90078)

IB1 and IB2 can be used for providing currents to external sensors, such as RTDs or bridge sensors. 100µA to 1000µA, in steps of 100µA, can be sourced by programming the ADC_AUXCN: RTD_CUR_SEL bits.

Refer to 3–Wire RTD to see how IB1 and IB2 can be used to source a 3-wire RTD.

9.4.2.2 Burnout Currents

As shown in Figure 52, the LMP900xx contains two internal 10 µA burnout current sources, one sourcing current from V_A to V_INP, and the other sinking current from V_INN to ground. These currents are used for sensor diagnostics and can be enabled for each channel using the CHx_INPUTCN: BURNOUT_EN bit.

Figure 52. Burnout Currents

9.4.2.2.1 Burnout Current Injection

Burnout currents are injected differently depending on the channel scan mode selected.

When BURNOUT_EN = 1 and the device is operating in ScanMode0, 1, or 2, the burnout currents are injected into all the channels for which the BURNOUT_EN bit is selected. This will cause problems and hence in this mode, more than one channel should not have its BURNOUT_EN bit selected. Also, the burnout current will interfere with the signal and introduce a fixed error depending on the particular external sensor.

When BURNOUT_EN = 1 and the device is operating in ScanMode3, burnout currents are injected into the last sampled channel on a cyclical basis (Figure 53). In this mode, burnout currents injection is truly done in the background without affecting the accuracy of the on-going conversion. Operating in this mode is recommended.

Figure 53. Burnout Currents Injection for Scanmode3

9.4.2.3 Sensor Diagnostic Flags

Burnout currents can be used to verify that an external sensor is still operational before attempting to make measurements on that channel. A non-operational sensor means that there is a possibility the connection between the sensor and the LMP900xx is open circuited, short circuited, shorted to V_A or GND, overloaded, or the reference may be absent. The sensor diagnostic flags diagram can be seen in Figure 54.

Figure 54. Sensor Diagnostic Flags Diagram

The sensor diagnostic flags are located in the SENDIAG_FLAGS register and are described in further details below.

9.5.1.1 Register Address (ADDR)

All registers are memory-mapped. A register address (ADDR) is composed of an upper register address (URA) and lower register address (LRA) as shown in Table 5. For example, ADDR 0x3A has URA=0x3 and LRA=0xA.

9.5.1.2 Register Read/Write Protocol

Figure 55 shows the protocol how to write to or read from a register.

Transaction 1 sets up the upper register address (URA) where the user wants to start the register-write or register-read.

Transaction 2 sets the lower register address (LRA) and includes the Data Byte(s), which contains the incoming data from the master or outgoing data from the LMP900xx.

Examples of register-reads or register-writes can be found in Register Read/Write Examples.

Figure 55. Register Read/Write Protocol

9.5.1.3 Streaming

When writing/reading 3+ bytes, the user must operate the device in Normal Streaming mode or Controlled Streaming mode. In the Normal Streaming mode, which is the default mode, data runs continuously starting from ADDR until CSB deasserts. This mode is especially useful when programming all the configuration registers in a single transaction. See the Normal Streaming Example section for an example of the Normal Streaming mode.

In the Controlled Streaming mode, data runs continuously starting from ADDR until the data has run through all (STRM_RANGE + 1) registers. For example, if the starting ADDR is 0x1C, STRM_RANGE = 5, then data will be written to or read from the following ADDRs: 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21. Once the data reaches ADDR 0x21, LMP900xx will wrap back to ADDR 0x1C and repeat this process until CSB deasserts. See the Controlled Streaming Example section for an example of the Controlled Streaming mode.

If streaming reaches ADDR 0x7F, then it will wrap back to ADDR 0x00. Furthermore, reading back the Upper Register Address after streaming will report the Upper Register Address at the start of streaming, not the Upper Register Address at the end of streaming.

To stream, write 0x3 to INST2’s SZ bits as seen in Figure 55. To select the stream type, program the SPI_STREAMCN: STRM_TYPE bit. The STRM_RANGE can also be programmed in the same register.

9.5.1.4 CSB – Chip Select Bar

An SPI transaction begins when the master asserts (active low) CSB and ends when the master deasserts (active high) CSB. Each transaction might be separated by a subsequent one with a CSB deassertion, but this is optional. Once CSB is asserted, it must not pulse (deassert and assert again) during a (desired) transaction.

CSB can be grounded in systems where LMP900xx is the only SPI slave. This frees the software from handling the CSB. Care has to be taken to avoid any false edge on SCLK, and while operating in this mode, the streaming transaction should not be used because exiting from this mode can only be done through a CSB deassertion.

9.5.1.5 SPI Reset

SPI Reset resets the SPI-Protocol State Machine by monitoring the SDI for at least 73 consecutive 1's at each SCLK rising edge. After an SPI Reset, SDI is monitored for a possible Write Instruction at each SCLK rising edge.

SPI Reset will reset the Upper Address Register (URA) to 0, but the register contents are not reset.

By default, SPI reset is disabled, but it can be enabled by writing 0x01 to SPI Reset Register (ADDR 0x02).

9.5.1.6 DRDYB - Data Ready Bar

DRDYB is a signal generated by the LMP900xx that indicates a fresh conversion data is available in the ADC_DOUT registers.

DRDYB is automatically asserted every (1/ODR) second as seen in Figure 56. Before the next assertion, DRDYB will pulse for t_DRDYB second. The value for t_DRDYB can be found in Timing Requirements.

Figure 56. DRDYB Behavior

If ADC_DOUT is being read while a new ADC_DOUT becomes available, then the ADC_DOUT that is being read is still valid (Figure 57). DRDYB will still be deasserted every 1/ODR second, but a consecutive read on the ADC_DOUT register will fetch the newly converted data available.

Figure 57. DRDYB Behavior For An Incomplete ADC_DOUT Reading

DRDYB can also be accessed via registers using the DT_AVAIL_B bit. This bit indicates when fresh conversion data is available in the ADC_DOUT registers. If new conversion data is available, then DT_AVAIL_B = 0; otherwise, DT_AVAIL_B = 1.

A complete reading for DT_AVAIL_B occurs when the MSB of ADC_DOUTH is read out. This bit cannot be reset even if REG_AND_CNV_RST = 0xC3.

9.5.1.6.1 DrdybCase1: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x00

Figure 58. DrdybCase1 Connection Diagram

As shown in Figure 58, the DRDYB signal and SDO can be multiplexed on the same pin as their functions are mostly complementary. In fact, this is the default mode for the SDO/DRDYB pin.

Figure 59 shows a timing protocol for DrdybCase1. In this case, start by asserting CSB first to monitor a DRDYB assertion. When the DRDYB signal asserts, begin writing the Instruction Bytes (INST1, UAB, INST2) to read from or write to registers. Note that INST1 and UAB are omitted from the figure below because this transaction is only required if a new UAB needs to be implemented.

While the CSB is asserted, DRDYB is driving the SDO/DRDYB pin unless the device is reading data, in which case, SDO will be driving the pin. If CSB is deasserted, then the SDO/DRDYB pin is High-Z.

Figure 59. Timing Protocol for DrdybCase1

9.5.1.6.2 DrdybCase2: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x03

SDO/DRDYB can be made independent of CSB by setting SDO_DRDYB_DRIVER = 0x03 in the SPI Handshake Control register. In this case, DRDYB will drive the pin unless the device is reading data, independent of the state of CSB. SDO will drive the pin when CSB is asserted and the device is reading data.

With this scheme, one can use SDO/DRDYB as a true interrupt source, independent of the state of CSB. But this scheme can only be used when the LMP900xx is the only device connected to the master's SPI bus because the SDO/DRDYB pin will be DRDYB even when CSB is deasserted.

The timing protocol for this case can be seen in Figure 60. When DRDYB asserts, assert CSB to start the SPI transaction and begin writing the Instruction Bytes (INST1, UAB, INST2) to read from or write to registers.

Figure 60. Timing Protocol For DrdybCase2

9.5.1.6.3 DrdybCase3: Routing DRDYB to D6

Figure 61. DrdybCase3 Connection Diagram

The DRDYB signal can be routed to pin D6 by setting SPI_DRDYB_D6 high and SDO_DRDYB_DRIVER to 0x4. This is the behavior for DrdybCase3 as shown in Figure 61.

The timing protocol for this case can be seen in Figure 62. Since DRDYB is separated from SDO, it can be monitored using the interrupt or polling method. If polled, the DRDYB signal needs to be polled faster than t_DRDYB to detect a DRDYB assertion. When DRDYB asserts, assert CSB to start the SPI transaction and begin writing the Instruction Bytes (INST1, UAB, INST2) to read from or write to registers.

Figure 62. Timing Protocol for DrdybCase3

9.5.1.7 Data Only Read Transaction

In a data only read transaction, one can directly access the data byte(s) as soon as the CSB is asserted without having to send any instruction byte. This is useful as it brings down the latency as well as the overhead associated with the instruction byte (as well as the Upper Address Byte, if any).

In order to use the data only transaction, the device must be placed in the data first mode. The following table lists transaction formats for placing the device in and out of the data first mode and reading the mode status.

Note that while being in the data first mode, once the data bytes in the data only read transaction are sent out, the device is ready to start on any normal (non-data-only) transaction including the Disable Data First Mode Instruction. The current status of the data first mode (enabled/disabled status) can be read back using the Read Mode Status Transaction. This transaction consists of the Read Mode Status Instruction followed by a single data byte (driven by the device). The data first mode status is available on bit [1] of this data byte.

The data only read transaction allows reading up to eight consecutive registers, starting from any start address. Usually, the start address will be the address of the most significant byte of conversion data, but it could just as well be any other address. The start address and number of bytes to be read during the data only read transaction can be programmed using the DATA_ONLY_1 AND DATA_ONLY_2 registers respectively.

The upper register address is unaffected by a data only read transaction. That is, it retains its setting even after encountering a data only transaction. The data only transaction uses its own address (including the upper address) from the DATA_ONLY_1 register. When in the data first mode, the SCLK must stop high before entering the Data Only Read Transaction; this transaction should be completed before the next scheduled DRDYB deassertion.

9.5.1.8 Cyclic Redundancy Check (CRC)

CRC can be used to ensure integrity of data read from LMP900xx. To enable CRC, set EN_CRC high. Once CRC is enabled, the CRC value is calculated and stored in SPI_CRC_DAT so that the master device can periodically read for data comparison. The CRC is automatically reset when CSB or DRDYB is deasserted.

The CRC polynomial is x⁸ + x⁵ + x⁴ + 1. The reset value of the SPI_CRC_DAT register is zero, and the final value is ones-complemented before it is sent out. Note that CRC computation only includes the bits sent out on SDO and does not include the bits of the SPI_CRC_DAT itself; thus it is okay to read SPI_CRC_DAT repeatedly.

The DRDYB signal normally deasserts (active high) every 1/ODR second. However, this behavior can be changed so that DRDYB deassertion can occur after SPI_CRC_DAT is read, but not later than normal DRDYB deassertion which occurs at every 1/ODR seconds. This is done by setting bit DRDYB_AFT_CRC high.

The timing protocol for CRC can be found in Figure 63.

Figure 63. Timing Protocol for Reading SPI_CRC_DAT

If SPI_CRC_DAT read extends beyond the normal DRDYB deassertion at every 1/ODR seconds, then CRC_RST has to be set in the SPI Data Ready Bar Control Register. This is done to avoid a CRC reset at the DRDYB deassertion. Timing protocol for reading CRC with CRC_RST set is shown in Figure 64.

Figure 64. Timing Protocol for Reading SPI_CRC_DAT Beyond Normal DRDYB Deassertion at Every 1/ODR Seconds

Follow the steps below to enable CRC:

1. Set SPI_CRC_CN = 1 (register 0x13, bit 4) to enable CRC.
2. Set DRDYB_AFT_CRC = 1 (register 0x13, bit 2) to dessert the DRDYB after CRC.
3. Compute the CRC externally, which should include ADC_DOUTH and ADC_DOUTL.
4. Collect the data and verify the reported CRC matches with the computed CRC (step above).

9.5.3.1 Writing to Register Examples

Using the register read/write protocol shown in Figure 55, the following example shows how to write three data bytes starting at register address (ADDR) 0x1F. After the last byte has been written to ADDR 0x21, deassert CSB to end the register-write.

Figure 65. Register-Write Example 1

The next example shows how to write one data byte to ADDR 0x12. Since the URA for this example is the same as the last example, transaction 1 can be omitted.

Figure 66. Register-Write Example 2

9.5.3.2 Reading from Register Example

The following example shows how to read two bytes. The first byte will be read from starting ADDR 0x24, and the second byte will be read from ADDR 0x25.

Figure 67. Register-Read Example

9.5.4.1 Normal Streaming Example

This example shows how to write six data bytes starting at ADDR 0x28 using the Normal Streaming mode. Because the default STRM_TYPE is the Normal Streaming mode, setting up the SPI_STREAMCN register can be omitted.

Figure 68. Normal Streaming Example

9.5.4.2 Controlled Streaming Example

This example shows how to read the 16-bit conversion data (ADC_DOUT) four times using the Controlled Streaming mode. The ADC_DOUT registers consist of ADC_DOUTH at ADDR 0x1A and ADC_DOUTL at ADDR 0x1B.

The first step (Figure 69) sets up the SPI_STREAMCN register. This step enters the Controlled Streaming mode by setting STRM_TYPE high in ADDR 0x03. Since two registers (ADDR 0x1A - 0x1B) need to be read, the STRM_RANGE is 1.

Figure 69. Setting Up SPI_STREAMCN

The next step shows how to perform the Controlled Streaming mode so that the master device will read ADC_DOUT from ADDR 0x1A and 0x1B, then wrap back to ADDR 0x1A, and repeat this process for four times. After this process, deassert CSB to end the Controlled Streaming mode.

Figure 70. Controlled Streaming Example

Table 8. RESTCN

Table 9. SPI_RESET

Table 10. PWRCN

Table 11. ADC_RESTART

Table 12. ADC_AUXCN

Table 13. ADC_DONE

Table 14. ADC_DOUT ⁽¹⁾

Table 15. CH_STS

Table 16. CH_SCAN ⁽¹⁾

Table 17. CHx_INPUTCN

Table 18. Default VIN for CH0-CH6

Table 19. CHx_CONFIG

Table 20. BGCALCN

Table 21. SCALCN

Table 22. CHx_SCAL_OFFSET

Table 23. CHx_SCAL_GAIN

Table 24. CHx_SCAL_SCALING

Table 25. CHx_SCAL_BITS_SELECTOR

Table 26. SENDIAG_THLD

Table 27. SENDIAG_FLAGS

Table 28. SPI_HANDSHAKECN

Table 29. SPI_STREAMCN

Table 30. DATA_ONLY_1

Table 31. DATA_ONLY_2

Table 32. SPI_DRDYBCN

Table 33. SPI_CRC_CN

Table 34. SPI_CRC_DAT

Table 35. GPIO_DIRCN

Table 36. GPIO_DAT