9.1.1 Op Amp: Input Stage

The PGA op amp is a rail-to-rail input and output (RRIO) single-supply op amp. The input topology uses two separate input stages in parallel to achieve rail-to-rail input. As Figure 66 shows, there is a PMOS transistor on each input for operation down to ground; there is also an NMOS transistor on each input in parallel for operation to the positive supply rail. When the common-mode input voltage (that is, the single-ended input, because this PGA is configured internally for noninverting gain) crosses a level that is typically about 1.5 V less than the positive supply, there is a transition between the NMOS and PMOS transistors. The result of this transition appears as a small input offset voltage transition that is reflected to the output by the selected PGA gain. This transition may be either increasing or decreasing, and differs from part to part as described in Figure 67 and Figure 68. These figures illustrate possible differences in input offset voltage between two different devices when used with AV_DD = 5 V. Because the exact transition region varies from device to device, the Electrical Characteristics: VS = AVDD = DVDD = 5 V table specifies an input offset voltage above and below this input transition region.

Figure 66. PGA Rail-To-Rail Input Stage

Figure 67. V_OS Versus Input Voltage—Case 1

Figure 68. V_OS Versus Input Voltage—Case 2

9.1.2 Op Amp: General Gain Equations

Figure 69 shows the basic configuration for using the PGA as a gain block. V_OUT / V_IN is the selected noninverting gain, depending on the model selected, for either binary or scope gains.

Figure 69. PGA Used as a Gain Block

Equation 1.

where

• G = 1, 2, 4, 8, 16, 32, 64, and 128 (binary gains)
• G = 1, 2, 5, 10, 20, 50, 100, and 200 (scope gains)

Figure 70 shows the PGA configuration and gain equations for V_REF = AV_DD/2. V_OUT0 is V_OUT when CH0 is selected and V_OUT1 is V_OUT when CH1 is selected. Notice the V_REF pin has no effect for G = 1 because the internal feedback resistor, R_F, is shorted out. This configuration allows for positive and negative voltage excursions around a midsupply virtual ground.

Figure 70. PGA112 and PGA113 Configuration for Positive and Negative Excursions Around Midsupply Virtual Ground

Equation 2.

When: G = 1

Then: V_OUT0 = G × V_IN0

Equation 3.

where

• G = 1, 2, 4, 8, 16, 32, 64, and 128 (binary gains)
• G = 1, 2, 5, 10, 20, 50, 100, and 200 (scope gains)

Table 7 details the internal typical values for the op amp internal feedback resistor (R_F) and op amp internal input resistor (R_I) for both binary and scope gains.

9.1.3 Op Amp: Frequency Response Versus Gain

Table 8 documents how small-signal bandwidth and slew rate change correspond to changes in PGA gain.

Full power bandwidth (that is, the highest frequency that a sine wave can pass through the PGA for a given gain) is related to slew rate by Equation 4:

Equation 4.

where

• SR = Slew rate in V/μs
• f = Frequency in Hz
• V_OP = Output peak voltage in volts

9.1.4 Analog MUX

The analog input MUX provides two input channels for the PGA112 and PGA113 devices and 10 input channels for the PGA116 and PGA117 devices. The MUX switches are designed to be break-before-make and thereby eliminate any concerns about shorting the two input signal sources together.

Four internal MUX CAL channels are included in the analog MUX for ease of system calibration. These CAL channels allow ADC gain and offset errors to be calibrated out. This calibration does not remove the offset and gain errors of the PGA for gains greater than 1, but most systems should see a significant increase in the ADC accuracy. In addition, these CAL channels can be used by the ADC to read the minimum and maximum possible voltages from the PGA. With these minimum and maximum levels known, the system architecture can be designed to indicate an out-of-range condition on the measured analog input signals if these levels are ever measured.

To use the CAL channels, V_CAL/CH0 must be permanently connected to the system ADC reference. There is a typical 100-kΩ load from V_CAL/CH0 to ground. Table 9 illustrates how to use the CAL channels with V_REF = ground. Table 10 describes how to use the CAL channels with V_REF = AV_DD/2. The V_REF pin must be connected to a source that is low-impedance for both DC and AC to maintain gain and nonlinearity accuracy. Worst-case current demand on the V_REF pin occurs when G = 1 because there is a 3.25-kΩ resistor between V_OUT and V_REF. For a 5-V system with AV_DD/2 = 2.5 V, the V_REF pin buffer must source and sink 2.5 V/3.25 kΩ = 0.7 mA minimum for a V_OUT that can swing from ground to 5 V.

Figure 71. Using CAL Channels With V_REF = Ground

Figure 72. Using CAL Channels With V_REF = AV_DD/2

9.1.5 System Calibration Using The PGA

Analog-to-digital converters (ADCs) contain two major errors that can be easily removed by calibration at a system level. These errors are gain error and offset error, as shown in Figure 73. Figure 73 shows a typical transfer function for a 12-bit ADC. The analog input is on the x-axis with a range from 0 V to (V_{REF_ADC} – 1LSB), where V_{REF_ADC} is the ADC reference voltage. The y-axis is the hexadecimal equivalent of the digital codes that result from ADC conversions. The dotted red line represents an ideal transfer function with 0000h representing 0 V analog input and 0FFFh representing an analog input of (V_{REF_ADC} – 1LSB). The solid blue line illustrates the offset error. Although the solid blue line includes both offset error and gain error, at an analog input of 0 V the offset error voltage, V_{Z_ACTUAL}, can be measured. The dashed black line represents the transfer function with gain error. The dashed black line is equivalent to the solid blue line without the offset error, and can be measured and computed using V_{Z_ACTUAL} and V_{Z_IDEAL}. The difference between the dashed black line and the dotted red line is the gain error. Gain and offset error can be computed by taking zero input and full-scale input readings. Using these error calculations, compute a calibrated ADC reading to remove the ADC gain and offset error.

Figure 73. ADC Offset and Gain Error

In practice, the zero input (0 V) or full-scale input (V_{REF_ADC} – 1LSB) of ADCs cannot always be measured because of internal offset error and gain error. However, if measurements are made very close to the full-scale input and the zero input, both zero and full-scale can be calibrated very accurately with the assumption of linearity from the calibration points to the desired end points of the ADC ideal transfer function. For the zero calibration, choose 10%V_{REF_ADC}; this value should be above the internal offset error and sufficiently out of the noise floor range of the ADC. For the gain calibration, choose 90%V_{REF_ADC}; this value should be less than the internal gain error and sufficiently below the tolerance of V_REF. These key points can be summarized in this way:

For zero calibration:

• The ADC cannot read the ideal zero because of offset error
• Must be far enough above ground to be above noise floor and ADC offset error
• Therefore, choose 10%V_{REF_ADC} for zero calibration

For gain calibration:

• The ADC cannot read the ideal full-scale because of gain error
• Must be far enough below full-scale to be below the V_REF tolerance and ADC gain error
• Therefore, choose 90%V_{REF_ADC} for gain calibration

The 12-bit ADC example in Figure 74 illustrates the technique for calibrating an ADC using a 10%V_{REF_ADC} and 90%V_{REF_ADC} reading where V_{REF_ADC} is the ADC reference voltage. The 10%V_REF reading also contains a gain error because it is not a V_IN = 0 calibration point. First, use the 90%V_REF and 10%V_REF points to compute the measured gain error. The measured gain error is then used to remove the gain error from the 10%V_REF reading, giving a measured 10%V_REF number. The measured 10%V_REF number is used to compute the measured offset error.

Figure 74. 12-Bit Example of ADC Calibration for Gain and Offset Error

The gain error and offset error in ADC readings can be calibrated by using 10%V_{REF_ADC} and 90%V_{REF_ADC} calibration points. Because the calibration is ratiometric to V_{REF_ADC}, the exact value of V_{REF_ADC} does not need to be known in the end application.

Follow these steps to compute a calibrated ADC reading:

1. Take the ADC reading at V_IN = 90% × V_REF and V_IN = 10% × V_REF. The ADC readings for 10%V_REF and 90%V_REF are taken.
Equation 5.
Equation 6.
Equation 7.
Equation 8.
2. Compute the ADC measured gain. The slope of the curve connecting the measured 10%V_REF and measured 90%V_REF point is computed and compared to the slope between the ideal 10%V_REF and ideal 90%V_REF. This result is the measured gain.
Equation 9.
3. Compute the ADC measured offset. The measured offset is computed by taking the difference between the measured 10%V_REF and the (ideal 10%V_REF) × (measured gain).
Equation 10.
4. Compute the calibrated ADC readings.
Equation 11.
Equation 12.

Any ADC reading can therefore be calibrated by removing the gain error and offset error. The measured offset is subtracted from the ADC reading and then divided by the measured gain to give a corrected reading. If this calibration is performed on a timed basis, relative to the specific application, gain and offset error over temperature are also removed from the ADC reading by calibration.

For example; given:

• 12-Bit ADC
• ADC Gain Error = 6 LSB
• ADC Offset Error = 4 LSB
• ADC Reference (V_{REF_ADC}) = 5 V
• Temperature = 25°C

Table 11 shows the resulting system accuracy.

9.1.6 Driving and Interfacing to ADCs

CDAC SAR ADCs contain an input sampling capacitor, C_SH, to sample the input signal during a sample period as shown in Figure 75. After the sample period, C_SH is removed from the input signal. Subsequent comparisons of the charge stored on C_SH are performed during the ADC conversion process. To achieve optimal op amp stability, input signal settling, and the demands for charge from the input signal conditioning circuitry, most ADC applications are optimized by the use of a resistor (R_FILT) and capacitor (C_FILT) filter placed between the op amp output and ADC input. For the PGA112 and PGA113 devices, or the PGA116 and PGA117 devices, setting C_FILT = 1 nF and R_FILT = 100 Ω yields optimum system performance for sampling converters operating at speeds up to 500 kHz, depending upon the application settling time and accuracy requirements.

Figure 75. Driving and Interfacing to ADCs

9.1.7 Power Supplies

Figure 76 shows a typical mixed-supply voltage system where the analog supply, AV_DD, is 5 V and the digital supply voltage, DV_DD, is 3 V. The analog output stage of the PGA and the SPI interface digital circuitry are both powered from DV_DD. When considering the power required for DV_DD, use the Electrical Characteristics: VS = AVDD = DVDD = 5 V table and add any load current anticipated on V_OUT; this load current must be provided by DV_DD. This split-supply architecture ensures compatible logic levels with the microcontroller. It also ensures that the PGA output cannot run the input for the onboard ADC into an overvoltage condition; this condition could cause device latch-up and system lock-up, and require power-supply sequencing. Each supply pin should be individually bypassed with a 0.1 μF ceramic capacitor directly at the device to ground. If there is only one power supply in the system, AV_DD and DV_DD can both be connected to the same supply; however, TI recommends using individual bypass capacitors directly at each respective supply pin to a single point ground. V_OUT is diode-clamped to AV_DD (as shown in Figure 76); therefore, set DV_DD less than or equal to AV_DD + 0.3 V. DV_DD and AV_DD must be within the operating voltage range of 2.2 V to 5.5 V.

At initial power-on, the state of the PGA is G = 1 and Channel 0 active.

9.1.8 Shutdown and Power-On-Reset (POR)

The PGA112 and PGA113 devices have a software shutdown mode, and the PGA116 and PGA117 devices offer both a hardware and software shutdown mode. When the PGA11x is shut down, it goes into a low-power standby mode. The Electrical Characteristics: VS = AVDD = DVDD = 5 V table details the current draw in shutdown mode with and without the SPI interface being clocked. In shutdown mode, R_F and R_I remain connected between V_OUT and V_REF.

When DV_DD is less than 1.6 V, the digital interface is disabled and the channel and gain selections are held to the respective POR states of Gain = 1 and Channel = V_CAL/CH0. When DV_DD is above 1.8 V, the digital interface is enabled and the POR gain and channel states remain unchanged until a valid SPI communication is received.

Figure 76. Split Power-Supply Architecture: AV_DD ≠ Dv_DD

Figure 77. PGA112, PGA113 (VSSOP-10) Typical Application Schematic

9.1.9 Typical Connections: PGA116, PGA117 (TSSOP-20)

Figure 78. PGA116, PGA117 (TSSOP-20)

9.2.1 Bipolar Input to Single-Supply Scaling

Figure 79. Bipolar to Single-Ended Input Algorithm

9.2.1.3 Application Curve

Figure 80. Voltage (V) vs Time (s)

9.2.2 Typical Application: General-Purpose Input Scaling

Figure 81 is an example application that demonstrates the flexibility of the PGA for general-purpose input scaling. V_IN0 is a ±100-mV input that is ac-coupled into CH0. The PGA112 and PGA113 are powered from a 5-V supply voltage, V_S, and configured with the V_REF pin connected to V_S/2 (2.5 V). V_CH0 is the ±100-mV input, level-shifted and centered on V_S/2 (2.5 V). A gain of 20 is applied to CH0, and because of the PGA113 configuration, the output voltage at V_OUT is ±2 V centered on V_S/2 (2.5 V).

CH1 is set to G = 1; through a resistive divider and scalar network, we can read ±5 V or 0 V. This setting provides bipolar to single-ended input scaling. Table 12 summarizes the scaling resistor values for R_A, R_X, and R_B for different ADC Ref voltages. V_{REF_ADC} is the reference voltage used for the ADC connected to the PGA112 and PGA113 output. It is assumed the ADC input range is 0 V to V_{REF_ADC}. The Table 12 section gives the algorithm to compute resistor values for references not listed in Table 12. As a general guideline, R_B should be chosen such that the input on-channel current multiplied by R_B is less than or equal to the input offset voltage. This value ensures that the scaling network contributes no more error than the input offset voltage. Individual applications may require other design trade-offs.

Figure 81. General-Purpose Input Scaling