Table 1. Design Requirements for a 12V, 100A, 5500µF Hot Swap Design

10.2.3.1 Select R_SNS and V_SNS,CL Setting

TPS2477x has a programmable V_SNS,CL with a recommended range of 10 mV to 67.5 mV. It can be used with a V_SNS,CL up to 200 mV, but that requires a resistor between SET and SENM to ensure stability of an internal loop. This is shown in Figure 19. R_STBL can be computed using the equation below.

Equation 10.

For high power applications a lower V_SNS,CL leads to better efficiency so 20 mV is targeted for this design. Targeting a current limit of 110A to allow margin for the load, the sense resistor can be calculated as follows:

Equation 11.

Since 0.18 mΩ resistors aren’t available, the closest standard resistor should be chosen. To have better efficiency, three 0.5mΩ resistors are used in parallel. Next the V_SNS,CL should be computed based on the actual R_SNS and then used to compute R_SET and R_IMON. R_SET is chosen to target 250 µA of current through SET and IMON pins during current limit.

Equation 12.

Equation 13.

Chose R_SET to equal 73.2 Ω, which is the closest available standard resistor. Next obtain the calculated R_IMON (R_IMON,CLC) as follows:

Equation 14.

Choose 2.67kΩ resistor for R_IMON, which is the closest available standard resistor. Since accurate current monitoring is not needed a 2512 2 terminal sense resistor can be used.

Finally, compute the actual current limit (I_LIM,CL) and the analog current monitoring scaling factor V_IMON,GAIN (V_IMON vs I_LOAD)

Equation 15.

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Equation 16.

Figure 19. Adding R_STBL for V_SNS,CL > 67.5mV

10.2.3.2 Selecting the Fast Trip Threshold and Filtering

The TPS2477x allows the user to program the fast trip threshold. When this threshold is exceeded the gate is quickly pulled down (<1µs). In addition C_FSTP can be added to include some filtering into the comparator. The selection of the fast trip threshold and filtering is influenced by the systems environment and requirements. In general, picking a larger threshold and larger filtering time will result in more immunity to nuisance trips, but also a slower response (possibly inadequate) to real fault conditions. It’s best to fine tune these threshold after testing the real system. As a starting point it is recommended to set the fast trip threshold at least 1.25x larger than then current limit. For this design example a 150A fast trip threshold along with a 500ns filtering time constant were targeted to ensure that the transient requirement will be passed. The value for R_FSTP and C_FSTP can be computed as shown below:

Equation 17.

sp

Equation 18.

The next closest standard resistor and capacitor values should be chosen. In this case R_FSTP = 249Ω and C_FSTP=2nF

10.2.3.3 Selecting the Hot Swap FET(s)

It is critical to select the correct MOSFET for a Hot Swap design. The device must meet the following requirements:

• The V_DS rating should be sufficient to handle the maximum system voltage along with any ringing caused by transients. For most 12V systems a 25 V or 30V FET is a good choice.
• The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.
• R_DSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to handle transients.
• Maximum continuous current rating should be above the maximum load current and the pulsed drain current must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three requirements will also pass these two.
• A V_GS rating of +16 V is required, because the TPS2477x can pull up the gate as high as 15.5 V above source.

For this design the CSD16415Q5B was selected for its low R_DSON and superior SOA. After selecting the MOSFET, the maximum steady state case temperature can be computed as follows:

Equation 19.

In the equation above n is the number of FETs used in parallel. For this example 4 FETS are used in parallel to prevent over- heating and improve efficiency. Note that the R_DSON is a strong function of junction temperature, which for most MOSFETS will be very close to the case temperature. A few iterations of the above equations may be necessary to converge on the final R_DSON and T_C,MAX value. According to the CSD16415Q5B datasheet, its R_DSON is about 1.3x greater at 100°C compared to room temperature . The equation below uses this R_DSON value to compute the T_C,MAX. Note that the computed T_C,MAX is close to the junction temperature assumed for R_DSON. Thus no further iterations are necessary. For this example an R_θCA of 50°C/W was used since there are 4 FETs close together and it’s expected that they will heat each other up. It’s highly recommended to test the board at full load and double check the thermals with the calculations.

Equation 20.

10.2.3.4 Select Power Limit

In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, at low power limit levels both the V_SNS and V_IMON become very low, which results in more error caused by offsets. It is recommended to keep V_SNS above 1.5mV and V_IMON above 27mV to ensure reasonable accuracy of the power limit engine. Based on these requirements the minimum power limit can be computed as shown below.

Equation 21.

In most applications the power limit can be set to P_LIM,MIN using the equation below. Here R_SNS and R_PWR are in Ωs and P_LIM is in Watts.

sp

Equation 22.

The closest available resistor should be selected. In this case it is a 118 kΩ.

10.2.3.5 Set Fault Timer

The inrush timer runs when the Hot Swap is in power limit or current limit, which is the case during start-up. Thus the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current limit (I_LIM x V_DS < P_LIM) the maximum start time can be computed with the equation below:

Equation 23.

For most designs (including this example) I_LIM,CL x V_DS > P_LIM so the Hot Swap will start in power limit and transition into current limit. In that case the maximum start time can be computed as follows:

Equation 24.

Note that the above start-time is based on typical current limit and power limit values. To ensure that the timer never times out during start-up it is recommended to set the fault time (TINR) to be 1.5x t_start,max or 6 ms. This will account for the variation in power limit, timer current, and timer capacitance.

Next the designer should decide if having equal TINR and TFLT is acceptable. Note that to pass the load transient the fault timer needs to be longer than 200 ms. If the inrush time is this long, it will place too much stress on the MOSFET during a start into short. For this reason, it’s ideal to have two separate timers. To ensure proper start up and to pass the load transient a target inrush time (T_INR,TGT) of 6 ms and a target fault time (T_FLT,TGT) of 250ms is used. C_INR,CLC and C_FLT,CLC is computed as follows:

Equation 25.

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Equation 26.

The next largest available C_INR is chosen as 47 nF and the next largest available C_FLT is chosen as 2.2µF

Next, the actual T_INR and T_FLT can be computed as shown below: Once the C_TMR is chosen the actual programmed time out can be computed as follows.

Equation 27.

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Equation 28.

10.2.3.6 Check MOSFET SOA

Once the power limit and fault timer are chosen, it’s critical to check that the FET will stay within its SOA during all test conditions. For this design example the TPS24772 is used, which does not retry during a hot-short. Thus the worst condition is a start-up into a short circuit. In this case the TPS24772 will start into a power limit and regulate at that point for 6.2 ms (T_INR). Based on the SOA of the CSD16415Q5B, it can handle 13 V, 15 A for 10 ms and it can handle 13 V, 100 A for 1 ms. The SOA for 6.2 ms can be extrapolated by approximating SOA vs time as a power function as shown below:

Equation 29.

Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be hotter during a start into a short. It is important to understand the hottest temperature that a MOSFET can be during a start-up (T_{C, MAX, START}). If a board has been off for a while and then it’s turned on T_{A, MAX} is a good estimate for T_{C,MAX, START}. However, if a board is on and then gets power cycled or a hot board is unplugged and plugged back in T_C,MAX should be used for T_C,MAX,START. This will depend on system requirements. For this design example it’s assumed that the board can only be plugged in cold and T_A,MAX is used to estimate T_C,MAX,START.

Equation 30.

Based on this calculation the MOSFET can handle 17 A, 13 V for 6.2 ms at 55°C elevated case temperature, but is only required to handle 9A during a start into short. Thus there is good margin and this will be a robust design. In general, it is recommended that the MOSFET can handle 1.3x more than what is required during a hot-short. This provides margin to cover the variance of the power limit and fault time.

10.2.3.7 Choose Under Voltage and Over Voltage Settings

The TPS2477x has comparators with 1.35V threshold on the ENHS, ENOR, and OV pins. A resistor divider can be used to set Undervoltage and Overvoltage thresholds for the bus. For this design example 10V and 14V were chosen as the limits to allow some margin for the 11V to 13V input bus. Once these limits are known, R_DIV2 and R_DIV3 can be computed using the equations below. R_DIV1 was set to 49.9 kΩ, which keeps the power consumption reasonable low without being too susceptible to leakage currents.

Equation 31.

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Equation 32.

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Equation 33.

Choose closest available resistors standard 1% resistors: R_DIV2 = 2.21 kΩ and R_DIV3 = 5.62 kΩ. The actual Under Voltage and Over Voltage settings can be computed for the chosen resistors as follows:

Equation 34.

sp

Equation 35.

10.2.3.8 Selecting C₁ and C_OUT

It is recommended to add ceramic bypass capacitors to help stabilize the voltages on the input and output. Since C_IN will be charged directly on hot-plug, its value should be kept small. 0.1µF is a good target. Since C_OUT doesn’t get charged during hot-plug, a larger value such as 1 µF could be used.

10.2.3.9 Adding C_ENHS

When the ENHS pin is pulled below its threshold and raised back up the IC will reset. Note that during a hot short the input voltage can easily droop below the UV threshold and cycle the ENHS pin. For the TPS24770 and TPS24771 ICs this will not change the behavior. However, when using the TPS24772 the cycling of the ENHS will result in the IC attempting to restart, which is undesired (this is the main reason why someone would use the TPS24772). To avoid this behavior a capacitor should be added to the ENHS to provide filtering. 33 nF was chosen for this example.

10.2.3.10 Selecting D1 and D2

During hot plug and hot short events there could be significant transients on the input and output of the Hot Swap that could cause operation outside of the IC specifications. To ensure reliable operation a TVS on the input and a Schottkey diode on the output are recommended. In this example a SMDJ14A and MBRS330T3G are used.

10.2.3.11 Checking Stability

For most applications, the TPS2477x is stable without any additional components. However in some cases additional C_GS,EXT is required as shown in the following figure to help stabilize the current and power limit loop. Typically this is for low current limits and low sense voltages. It is easy to check whether these extra components are needed using the equations below. Note that the transconductance (also referred to as gm and gfs) of the FET will vary based on the current and thus gm' is used in the equations as a normalizing parameter. The CSD16415Q5B has a gm of 168 siemens at 40A of I_DS, resulting in gm' of 26.56. For this example, C_GS,MIN (per FET) was computed to be 0.25nF, while the C_ISS of the CSD16415Q5B is 3.15nF providing plenty of margin for the design. In general it is recommended to have a 2x margin from the typical C_ISS and C_GS,MIN to account for any variation that the FET would have. If the C_ISS of the MOSFET isn't large enough an external RC should be added as shown in the figure below.

Equation 36.

Equation 37.

Equation 38.

Figure 20. Adding C_GS,EXT to Ensure Stability

10.2.3.12 Compute Tolerances

After finishing a design it is often desired to know the variations of each setting. Often times there are multiple error sources and there are two common ways to analyze the circuit. One is worst case, which adds all of the error sources and the other one is root sum square (RSS), which is less conservative. When error sources are independent, using the RSS method provides a more statistically accurate view of the tolerances. This method is used in this section. Note that the error calculations are quite long and tedious and it’s recommended to use TI’s excel tools, which support both worst case and RSS analysis. For this example the below tolerances are assumed. The following table lists the assumptions for the component tolerances. Note that the sense resistor itself is 1% accurate, but multiple two terminal 2512 resistors are used so additional error is introduced from solder resistance and layout limitations of paralleling resistors. For this example 3% is assumed as the total error of the sensing network.

First, the tolerance of the current monitoring and current limit is computed.

There are 5 error sourcing contributing to the current monitoring accuracy on the IMON pin: tolerance of R_SET (ER_SET), tolerance of R_IMON (ER_IMON), tolerance of R_SNS (E_RSNS), the IC gain error (ER_GAIN), and the IC offset error (ER_OS). All of these errors are in % with the exception of the offset error. To get a percent error due to the offset error (ER_OS%) simply divide the offset by the sense voltage. For the TPS2477x, ER_GAIN is 0.4%, and ER_OS is 150 µV.

Based on these values the full scale (I_FS,ERR,IMON) current monitoring accuracy at the Imon pin can be computed with the following equations.

Equation 39.

Note that the TPS2477x detects the current limit when the IMON pin exceeds 675 mV. Thus the current limit error I_LIM,ER is a combination of the I_FS,ERR,IMON and the current limit error at the I_MON pin (I_LIM,ERR,IMON). The 675 mV threshold varies up to 15 mV so I_LIM,ERR,IMON is 2.3% and the current limit error can be computed as follows:

Equation 40.

Next the power limit error is computed. This error is made up of three sources: the error from external components (ER_COMP), the error when translating the sense voltage to IMON (I_{PL,ERR, IMON}), and the error of the power limit engine at IMON (ER_IMON,PL). Both ER_SNS and ER_{IMON, PL} are a function of the operating point of the power limit engine. Note that this error is greatest at largest V_DS, since V_SNS,PL is smallest (refer to Figure 12). For this example V_DS is largest when V_IN = 13 V (maximum V_IN) and V_OUT = 0 V and the error is computed at this operating point. The sense voltage (V_SNS) and the voltage at the IMON pin (V_IMON) should be computed for this operating point using the equations below:

Equation 41.

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Equation 42.

The I_PL,ERR,IMON can be computed similarly to I_FS,ERR,IMON using the equation below.

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Equation 43.

The tolerance of the power limit engine is specified at three V_IMON points in the datasheet: 135 mV (±20.3 mV), 67.5 mV (±10.1 mV), and 27 mV (±8.1 mV). To get the % error at the real operating point, the absolute error should be extrapolated and divided by V_IMON as shown in the equation below. This is graphically depicted in Figure 23.

Equation 44.

Figure 21. Extrapolating Power Limit Error

Once ER_IMON,PL and I_PL,ERR,IMON are known the total power limit error (PL_ERR,TOT) can be computed using the equation below. The component error (3.5%) comes from R_SNS (3%), R_PLIM (1%), R_SET (1%), and R_IMON (1%).

Equation 45.

After computing the fast trip voltage threshold to be 24.9 mV (100 µA × 249 Ω), the fast trip threshold error resulting from the IC (FST_{ERR, IC}) can be computed using a similar extrapolation method as used for power limit. The component error of R_SNS and R_FST should be added to obtain the total fast trip error (FST_ERR,TOT). Both equations are shown below.

Equation 46.

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Equation 47.

The IC error of the UV / OV threshold is always 3.7% (0.05 V / 1.35 V). Assuming that all resistors have a 1% error the component error is 1.41% (2 resistors). When using the RSS method the total error is 4%. For the timer error, the IC contributes 22% and 10% comes from the component. When using the RSS method the total error becomes 24.2%.

The table below summarizes the final tolerances of the design:

10.2.5.1 Design Requirements

The following table summarizes the requirements for this design. Note that the output power cannot exceed 240W for more than 250 ms.

10.2.5.2 Theory of Operations

Before going into the details of the design it’s important to understand the impact that R_POW has on the circuit. Refer to Figure 31 for this discussion.

Figure 31. Impact of R_POW Resistor

Note that the TPS2477x detects overcurrent conditions when V_IMON reaches 675mV, which occurs when there is sufficient current (i_IMON) flowing through R_IMON. Also note that i_IMON is a sum of i_SET and i_POW. If i_IMON,CL, i_SET,CL, and i_POW,CL correspond to these same current when V_IMON reaches 675mV and TPS2477x detects current limit, the following equations can be written.

Equation 48.

Equation 49.

Also note that the amplifier ensures that SET and SENM are equal and thus I_LIM can be derived as follows:

Equation 50.

Equation 51.

Examining the equation above, it can be seen that I_LIM reduces as V_IN becomes larger. Note that the ultimate goal is to limit output power. However, when the FET is on, V_IN is very close to V_OUT and they can be assumed to be equal.

The figure below compares the ideal I_LIM vs V_OUT (I_LIM =240 W / V_OUT) profile to that of the R_POW implementation shown here. The error is large when the output voltage is far from 12V, but the performance is quite good near 12V. The next figure shows the effective output power limit for output voltages from 10 V to 14 V. It can be seen that the results are quite good and much better than using a simple 20A current limit, without the R_POW resistor to compensate for V_IN variation.

Figure 32. Current Limit (with R_POW) vs Output Voltage

Figure 33. Output Power Limiting using R_POW vs Standard ILIM

10.2.5.3 Design Procedure

10.2.5.3.1 Select V_SNS,CL, R_SNS, and R_SET Setting

For this example, V_SNS,CL of 10 mV was selected to optimize efficiency. Then R_SNS can be computed to 0.5mΩ. There is some flexibility in picking the R_SET value. In this case targeting 100 µA for I_SET,CL, R_SET is computed to be 100 Ω as shown in the following equation.

Equation 52.

10.2.5.3.1.1 Select R_POW and R_IMON

R_POW controls the slope of the I_LIM vs V_IN curve and thus the ideal slope should be found first before selecting R_POW. This can be done by taking the derivative of the ideal current limit (I_{LIM, IDEAL}) vs V_IN curve and evaluating it at 12V. This is found to be –1.667 A/V as shown in the equations below. Next the derivative of equation 51 is taken to isolate the terms that influence the slope of I_LIM vs V_IN curve. Since R_SET and R_SNS have already been selected, R_POW remains the only parameter that can be varied. Thus, R_POW is computed using the last equation below.

Equation 53.

Equation 54.

Equation 55.

The closest available standard resistor is chosen for R_POW, which is 121kΩ.

Next R_IMON should be chosen to ensure that the output power limit is 240 W at 12 V, which is the typical operating point. R_IMON is computed to be 3.49kΩ and the closest available standard resistor of 3.48 kΩ is chosen.

Equation 56.

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Equation 57.

10.2.5.3.1.2 Selecting the Hot Swap FET(s)

It is critical to select the correct MOSFET for a Hot Swap design. The device must meet the following requirements:

• The V_DS rating should be sufficient to handle the maximum system voltage along with any ringing caused by transients. For most 12V systems a 25 V or 30V FET is a good choice.
• The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.
• R_DSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to handle transients.
• Maximum continuous current rating should be above the maximum load current and the pulsed drain current must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three requirements will also pass these two.
• A V_GS rating of +16 V is required, because the TPS2477x can pull up the gate as high as 15.5 V above source.

For this design the CSD16415Q5B was selected for its low R_DSON and superior SOA. After selecting the MOSFET, the maximum steady state case temperature can be computed as follows:

Equation 58.

In the equation above n is the number of FETs used in parallel. Note that the R_DSON is a strong function of junction temperature, which for most MOSFETS will be very close to the case temperature. A few iterations of the above equations may be necessary to converge on the final R_DSON and T_C,MAX value. According to the CSD16415Q5B datasheet, its R_DSON is about 1.2 x greater at 75°C compared to room temperature. . The equation below uses this R_DSON value to compute the T_C,MAX. Note that the computed T_C,MAX is close to the junction temperature assumed for R_DSON. Thus no further iterations are necessary.

Equation 59.

10.2.5.3.1.3 Keeping MOSFET within SOA During Normal Start-up

Next, the designer must ensure that the MOSFET will stay within SOA during start-up and a start-up into short. Note that the TPS24772 (fast latch off) is used for this design so the MOSFET stress during a hot short is minimal.

Since R_POW biases the I_MON pin, it interferes with FET power limiting and it’s recommended to disable FET power limiting it by selecting a 4.99kΩ resistor for R_POW.

The inrush current can be limited by adding a capacitor from HGATE to GND (C_DVDT) as shown in the application diagram. This capacitor limits the slew rate of HGATE at start-up, which will in turn limit the slew rate of V_OUT. Assuming that the load is off until PGHS is asserted, all of the inrush current would be going into C_OUT and be inversely proportional to the slew rate of V_OUT. Refer to the application plots for a start-up waveform. In addition, a 1kΩ resistor is placed in series with C_DVDT to ensure that C_DVDT doesn’t slow down the short circuit response of the Hot Swap.

For this example, a 100 nF capacitor was used for C_DVDT. This results in an inrush current (I_INR) of 1.375A, total inrush time (t_INR) of 24.5, and peak FET power dissipation (P_FET,PEAK) of 18.7W as shown in equations below. This assumes maximum input voltage of 13.2 V

Equation 60.

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Equation 61.

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Equation 62.

Next, it’s importation to check that the MOSFET can handle this stress level. Note that the power dissipation of the MOSFET will start at P_INR,MAX and will reduce to zero as the V_DS drop across the MOSFET reduces. The effective stress on the MOSFET can be approximated to be P_INR,MAX for t_INR/2, which is the equivalent amount of energy. For this example, the FET stress is 18.7W for 12.3 ms. Looking at the SOA curve of the CSD16415Q5B, at V_DS of 13.2 V it can handle ~15A for 10ms or ~4A for 100ms. Using the same method as the previous design example, it can be computed that the MOSFET can handle 13.4A for 12.3 ms when V_DS=13.2 V.

The SOA of a MOSFET is specified at a case temperature of 25°C, while the real case temperature can be hotter during a start into a short. It is important to understand the hottest temperature that a MOSFET can be during a start-up (T_{C, MAX, START}). If a board has been off for a while and then it’s turned on, T_{A, MAX} is a good estimate for T_{C,MAX, START}. However, if a board is on and then gets power cycled or gets unplugged and plugged back in, T_C,MAX should be used for T_C,MAX,START. This will depend on system requirements. For this design example, it is assumed that a hot board can be power cycled or hot plugged and thus T_C,MAX is used to estimate T_C,MAX,START.

Equation 63.

Based on this calculation the MOSFET can handle 8.4 A, 13.2 V for 12.3 ms at 72°C elevated case temperature, but is only required to handle 1.375 A. Thus there is good margin and this will be a robust design. In general a 1.3x margin is recommended to cover for variations.

Next, the start into short case is considered. Since the MOSFET power limit is disabled, the current through the MOSFET will reach 20A before the part starts to regulate and runs the inrush timer. In order to minimize FET stress, a short inrush timer is chosen (1nF of C_INR). Unfortunately, when a very short timer is used and there is a dv/dt capacitor, the FET stress cannot be simply estimated by T_INR. In the following figure, it is clear that the FET has both voltage and significant current across it for longer than just T_INR. This occurs because TINR is only activated when IIN reaches the current limit threshold, which doesn’t happen immediately due to the slow dv/dt on the gate and the limited transconductance of the FET.

The current is not a square pulse, which makes it hard to compare the FET stress to the SOA curves. Thus the stress shown in the following figure needs to be converted to an equivalent square pulse. For this example, the equivalent pulse was assumed to be 20 A for 1ms. The MOSFET can handle 100A, 13.2 V for 1ms, which can be derated to 62 A when accounting for elevated case temperature. This provides plenty of margin and ensures a robust design.

Equation 64.

Figure 34. Start-up Into Short

10.2.5.3.1.4 Choose Fault Timer

To pass the load transient, a target fault time (T_FLT,TGT) of 250ms is used. C_FLT,CLC is computed as follows:

sp

Equation 65.

The next largest available C_FLT is chosen as 2.2µF, which results in a TFLT of 290ms as shown below.

Equation 66.

10.2.5.3.1.5 Choose Under Voltage and Over Voltage Settings

For this design example 10V and 14V were chosen as the limits to allow some margin for the 10.8V to 13.2V input bus. These are identical to the previous design example. See Choose Under Voltage and Over Voltage Settings section for programming these thresholds.

10.2.5.3.1.6 Selecting C_IN and C_OUT

It is recommended to add ceramic bypass capacitors to help stabilize the voltages on the input and output. Since C_IN will be charged directly on hot-plug, it’s value should be kept small. 0.1µF is a good target. Since C_OUT doesn’t get charged during hot-plug, a larger value such as 1 µF could be used.

10.2.5.3.1.7 Selecting D1 and D2

During hot plug and hot short events there could be significant transients on the input and output of the Hot Swap that could cause operation outside of the IC specifications. To ensure reliable operation a TVS on the input and a Schottkey diode on the output are recommended. In this example a SMDJ14A and MBRS330T3G are used.

10.2.5.3.1.8 Adding C_ENHS

When the ENHS pulled below its threshold and raised back up the IC will reset. Note that during a hot short the input voltage can easily droop below the UV threshold and cycle the ENHS pin. For the TPS24770 and TPS24771 ICs this will not change the behavior. However, when using the TPS24772 the cycling of the ENHS will result in the IC attempting to restart, which is undesired (this is the main reason why someone would use the TPS24772). To avoid this behavior a capacitor should be added to the ENHS to provide filtering. 33 nF was chosen for this example.

10.2.5.3.1.9 Stability Considerations

Since there is a 100nF C_DVDT attached to HGATE, this significantly increases the effective capacitance of HGATE and guarantees stability for this application.

10.2.5.4 Application Curves

Figure 35. No Load then Hot Short (Zoomed Out)

Figure 37. Overcurrent

Figure 39. Start up (C_OUT = 2500 µF)

Figure 41. Under Voltage and Over Voltage with V_IN Rising

Figure 36. Full Load then Hot Short (Zoomed In)

Figure 38. Start Up into Short

Figure 40. Start up showing PGHS and FLTb (C_OUT = 2500 µF)

10.2.6.1 Design Requirements

The following table summarizes the requirements for this design.

10.2.6.1.2 Selecting the Hot Swap FET(s)

It is critical to select the correct MOSFET for a Hot Swap design. The device must meet the following requirements:

• The V_DS rating should be sufficient to handle the maximum system voltage along with any ringing caused by transients. For most 12V systems a 25 V or 30V FET is a good choice.
• The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.
• R_DSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to handle transients.
• Maximum continuous current rating should be above the maximum load current and the pulsed drain current must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three requirements will also pass these two.
• A V_GS rating of +16 V is required, because the TPS2477x can pull up the gate as high as 15.5 V above source.

For this design the CSD17573Q5B was selected for its low R_DSON and great cost point. After selecting the MOSFET, the maximum steady state case temperature can be computed as follows:

Equation 67.

In the equation above n is the number of FETs used in parallel. Note that the R_DSON is a strong function of junction temperature, which for most MOSFETS will be very close to the case temperature. A few iterations of the above equations may be necessary to converge on the final R_DSON and T_C,MAX value. According to the CSD17573Q5B datasheet, its R_DSON is about 1.2 x greater at 65°C compared to room temperature. The equation below uses this R_DSON value to compute the T_C,MAX. Note that the computed T_C,MAX is close to the junction temperature assumed for R_DSON. Thus no further iterations are necessary.

Equation 68.

10.2.6.1.3 Keeping the MOSFET within SOA

As in the previous example, it is important to ensure that the MOSFET stays within its SOA during both regular start-up and start-up into short.

First consider the regular start-up. The same C_DVDT is used as the last example so the FET is required to handle 18.2W (or 1.38A and 13.2V) for 12.3 ms. Based on the SOA curve of the CSD17573Q55B, at V_DS of 13.2 V it can handle 4.5 A for 10 ms or 2 A for 100 ms. Using the same method as the previous design example, it can be inferred that the MOSFET can handle 4.2 A for 12.3 ms when V_DS=13.2 V.

The SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be hotter during a start into a short. It is important to understand the hottest temperature that a MOSFET can be during a start-up (T_{C, MAX, START}). If a board has been off for a while and then it’s turned on T_{A, MAX} is a good estimate for T_{C,MAX, START}. However, if a board is on and then gets power cycled T_C,MAX should be used for T_C,MAX,START. This will depend on system requirements. For this design example, it’s assumed that a hot board can be power cycled or hot plugged and T_C,MAX is used to estimate T_C,MAX,START.

Equation 69.

Based on this calculation the MOSFET can handle 2.7 A, 13.2 V for 12.3 ms at 69°C elevated case temperature, but is only required to handle 1.38 A. Thus there is sufficient margin to make this a robust design. Again a 1.3x margin is recommended to cover for variations.

Next, consider the start into short condition. Similar to the previous design the MOSFET would need to handle 20A and 13.2 V for ~1ms. Checking the SOA curve of the CSD17573Q5B, it can only handle 10A and 13.2 V for 1ms, so it’s SOA is clearly not sufficient.

This is where Q₂ and R_SET2 come in. They serve to reduce the current limit during starting up (I_LIM,START) while the V_DS of the Hot Swap MOSFET is above V_T of Q₂ (1V to 2V). The ratio of I_LIM to I_LIM,START, denoted as I_RATIO, is a function of R_SET and R_SET2 as shown below. For this example a ratio of 0.2 (I_LIM,START=4A) was targeted to reduce MOSFET stress, keep the current limit above I_INR, and ensure sufficient signal on V_SNS to keep the error reasonable. Once _IRATIO is chosen, R_SET2 is computed to be 25 Ω as shown below.

Equation 70.

Equation 71.

The start-up into short (with R_SET2 and Q₂) is shown in Figure 43 below. The equivalent power pulse is now 4A for ~0.5ms. The MOSFET can handle 10A, 13.2 V for 1ms, which can be derated to 6.5 A when accounting for elevated case temperature. Since the MOSFET is only required to handle 4A for 0.5ms there is plenty of margin in the design.

Equation 72.

Figure 43. Start-up Into Short (with R_SET and Q₂)

10.2.6.2 Q2 Selection

There is a lot of flexibility when selecting Q₂. Any PMOS with a ±20V V_GS rating and 20V of V_DS rating is sufficient. For this example IRLML5203PbF was used. Note that the 100k series resistor along with the C_ISS of Q2 (~500pF) for a filter with a 50 µs time constant. This protects Q₂ in case there is high frequency ringing on V_IN that causes V_IN – V_OUT to exceed 20V. This will usually happened during hot-plug or hot-short.

10.2.6.3 Application Curves

Figure 44. Full Load then Hot Short (Zoomed Out)

Figure 45. Full Load then Hot Short (Zoomed In)

Figure 46. Over Current

Figure 48. Start up (C_OUT = 2500 µF)

Figure 50.

Figure 47. Start Up Into Short

Figure 49. Start up showing PGHS and FLTb (C_OUT = 2500 µF)