ZHCSEO1C March 2012 – February 2016 TPS65177 , TPS65177A
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4
Device Functional Modes
- 7.4.1 Boost Converter (V(AVDD))
- 7.4.2 Buck 1 Converter (V(IO))
- 7.4.3 BUCK 2 CONVERTER (V(CORE))
- 7.4.4 Buck 3 Converter (V(HAVDD))
- 7.4.5 Positive Charge Pump Controller (V(GH)) with Temperature Compensation
- 7.4.6 Negative Charge Pump Controller (V(GL))
- 7.5 Gate Pulse Modulation (V(GHM))
- 7.6
Programming
- 7.6.1 I2C Serial Interface Description
- 7.6.2 Memory Description
- 7.6.3 Read / Write Description
- 7.6.4 Write Operation
- 7.6.5 READ OPERATION
- 7.6.6 Write Single Data to DAC:
- 7.6.7 Write Multiple Data to DAC (Auto Increment Address):
- 7.6.8 Write all DAC Data to EEPROM:
- 7.6.9 Read Single Data From DAC / EEPROM:
- 7.6.10 Read Multiple Data fFom DAC / EEPROM (Auto Increment Address):
- 7.7
Register Map
- 7.7.1
Registers and DAC Settings
- 7.7.1.1 Channel Register (with factory value) - 00h (00h)
- 7.7.1.2 Boost Output Voltage V(AVDD) Register (with factory value) - 01h (0Fh)
- 7.7.1.3 Boost HVS Offset Voltage Register (with factory value) - 02h (05h)
- 7.7.1.4 Boost Current Limit Negative Offset Current Register (with factory value) - 03h (00h)
- 7.7.1.5 Boost Soft-start Time Register (with factory value) - 04h (00h)
- 7.7.1.6 Buck 1 Output Voltage V(IO) Register (with factory value) - 05h (03h):
- 7.7.1.7 Buck 2 Output Voltage V(CORE) Register (with factory value) - 06h (02h)
- 7.7.1.8 Buck 3 Output Voltage V(HAVDD) Register (with factory value) - 07h (1Bh)
- 7.7.1.9 Pos. Charge Pump Low Output Voltage V(GH_L) Register (with factory value) - 08h (08h):
- 7.7.1.10 Positive Charge Pump Low Output Voltage V(GH_L) to V(GH_H) Positive Offset Voltage V(GH_OFS) Register (with factory value) - 09h (04h):
- 7.7.1.11 Gate Pulse Modulation Limit Voltage Register (with factory value) - 0Ah (00h)
- 7.7.1.12 Negative Charge Pump Output Voltage V(GL) Register (with factory value) - 0Bh (04h)
- 7.7.1.13 Buck 3 HVS Offset Voltage Register (with factory value) - 0Ch (00h):
- 7.7.1.14 Memory Write Remain Time Register (with factory value) - FEh (0Fh):
- 7.7.1
Registers and DAC Settings
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RHA|40
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7 Detailed Description
7.1 Overview
The TPS65177/A provides all supply rails needed by a GIP (Gate-in-Panel) or non-GIP TFT-LCD panel. All output voltages are I2C programmable.
V(IO) and V(CORE) for the T-CON, V(AVDD) and V(HAVDD) for the Source Driver and the Gamma Buffer, V(GH) and V(GL) for the Gate Driver or the Level Shifter. For use with non-GIP technology Gate Pulse Modulation (GPM) is implemented, for use with GIP technology the V(GH) rail can be temperature compensated. Furthermore a High Voltage Stress Mode (HVS) for V(AVDD) and V(HAVDD) and an integrated V(AVDD) Isolation Switch is implemented. V(CORE), V(HAVDD), V(GH), V(GL), GPM and the V(GH) temperature compensation can be enabled and disabled by I2C programming.
A single BOM (Bill of Materials) can cover several panel types and sizes whose desired output voltage levels can be programmed in production and stored in a non-volatile integrated memory.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Power-Up
When VI rises above the UVLO (undervoltage lockout) the device loads the stored values in the non-volatile Initial Value register into the volatile DAC register. When all data is written the power-up sequencing starts with enabling the buck 1 converter (V(IO)), which ramps up its output voltage in 3 ms. When the output is in regulation the buck 2 converter (V(CORE)) starts and ramps up its output voltage in 3 ms, when its output voltage is in regulation the negative charge pump controller starts and V(GL) is declining in typ. 1.5 ms until the output voltage is in regulation. In case V(GL) is driven by the boost switch pin (SW) V(GL) starts declining when the boost starts switching.
When the enable pin (EN) is pulled “high” the isolation switch closes smoothly so that after typ. 10 ms its output (V(AVDD)) is at VI level, then the boost converter (V(AVDD)) starts and its output voltage (V(AVDD)) ramps linearly in 10 ms or 20 ms (programmable by I2C) until it is in regulation. Then the positive charge pump controller starts and V(GH) is rising in typ. 1.5 ms until the output voltage is in regulation. To ensure proper sequencing even if EN is pulled “high” already at the beginning (e.g. connected to VI) the start of the boost converter V(AVDD) is blocked until V(GL) is Power Good or 2.5 ms have passed since V(GL) was enabled.
If the EN pin is not connected to VI, the device detects a collapsed V(AVDD) voltage about 40 ms after EN is pulled low. This function prevents the panel to restart without a proper power supply reset. The device partially shuts down as described in the Short-Circuit and Overload Protection section. The device is in a latched state and only a power cycle can restart the V(AVDD), V(HAVDD), V(GH) and V(GL) rail.
When V(GL) is driven by the boost switch pin (SW) the EN-pin should be connected to VI, otherwise V(GL) detects a short when EN is pulled low as the V(GL) voltage collapses. V(GL) collapses because the supporting switch node (SW) stops switching and the device partially shuts down as described in the Short-Circuit and Overload Protection section. The device is in a latched state and only a power cycle can restart the V(AVDD), V(HAVDD), V(GH) and V(GL) rail.
The buck 2 and buck 3 converter as the negative and positive charge pump controller can be disabled by I2C. If disabled they are skipped in the sequencing (e.g. disabled buck 2 → buck 1 is in regulation → start neg. CP).
The Gate Pulse Modulation block is disabled when VI is below UVLO or EN is “low” and enabled when V(GH) is in regulation. When the block is disabled by UVLO the high side switch of the Gate Pulse Modulation is turned on and the output VGHM is connected to the VGH pin, when the block is disabled by pulling the EN pin “low” the low side switch is turned on and the output VGHM is connected to the RE pin.
7.3.1.1 TPS65177
If the EN pin is not connected to VI, the device detects a collapsed V(AVDD) voltage about 40 ms after EN is pulled low. This function prevents the panel to restart without a proper power supply reset. The device partially shuts down as described in the Short-Circuit and Overload Protection section. The device is in a latched state and only a power cycle can restart the V(AVDD), V(HAVDD), V(GH) and V(GL) rail.
7.3.1.2 TPS65177A
The device can be restarted without a power cycle, however note that when V(GL) is driven by the boost switch pin (SW) the EN-pin should be connected to VI. If the EN-pin is not connected to VI the V(GL) protection detects a short when EN is pulled low as the V(GL) voltage collapses. V(GL) collapses because the supporting switch node (SW) stops switching and the device partially shuts down as described in the Short-Circuit and Overload Protection section. The device is in a latched state and only a power cycle can restart the V(AVDD), V(HAVDD), V(GH) and V(GL) rail.
Figure 10. TPS65177 Power-up Sequencing
Figure 11. TPS65177A Power-up Sequencing
7.3.2 Power-Down
When VI falls below the UVLO threshold all blocks are disabled and the discharge rate is given by the output load and the output capacitors. The Gate Pulse Modulation output V(GHM) follows V(GH).
7.3.3 Thermal Shutdown
A thermal shutdown is implemented to prevent damage because of excessive heat and power dissipation. Once a temperature of typically 150 ºC is exceeded the device shuts down and stays off. VI must fall below Undervoltage lockout threshold (UVLO) to reset the thermal shutdown.
7.3.4 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages an undervoltage lockout is included, which shuts down the device at voltages lower than typically 8.3 V.
7.3.5 Short-Circuit and Overload Protection
7.3.5.1 Boost Converter (V(AVDD)):
| When V(SWO) < 40% of its nominal value | → | Shut down Boost, Isolation Switch, Buck3, neg. and pos. Charge Pump controller (Buck 1 and Buck 2 keep working) → latched condition, only triggering UVLO enables the device again. |
| When V(SWO) < 80% of its nominal value for longer than 50 ms (overload) | → | Shut down Boost, Isolation Switch, Buck3, neg. and pos. Charge Pump controller (Buck 1 and Buck 2 keep working) → latched condition, only triggering UVLO enables the device again. |
7.3.5.2 Buck 1 Converter (V(IO)):
| When V(IO) < 40% of its nominal value | → | Shut down the whole device → latched condition, only triggering UVLO enables the device again. |
| When V(IO) < 80% of its nominal value for longer than 50 ms (overload) | → | Shut down the whole device → latched condition, only triggering UVLO enables the device again. |
7.3.5.3 Buck 2 Converter (V(CORE)):
| When V(CORE) < 40% of its nominal value | → | Shut down the whole device → latched condition, only triggering UVLO enables the device again. |
| When V(CORE) < 80% of its nominal value for longer than 50 ms (overload) | → | Shut down the whole device → latched condition, only triggering UVLO enables the device again. |
7.3.5.4 Buck 3 Converter (V(HAVDD)):
| When V(HAVDD) < 40% of its nominal value | → | Shut down Buck3, Isolation Switch, Boost, neg. and pos. Charge Pump controller (Buck 1 and Buck 2 keep working) → latched condition, only triggering UVLO enables the device again. |
| When V(HAVDD) < 80% of its nominal value for longer than 50 ms (overload) | → | Shut down Buck3, Isolation Switch, Boost, neg. and pos. Charge Pump controller (Buck 1 and Buck 2 keep working) → latched condition, only triggering UVLO enables the device again. |
7.3.5.5 Positive Charge-Pump Controller (V(GH)):
| When V(GH) < 40% of its nominal value | → | Shut down pos. Charge Pump, Isolation Switch, Boost, Buck3, neg. Charge Pump controller (Buck1 and Buck2 keep working) → latched condition, only triggering UVLO enables the device again. |
| When V(GH) < 80% of its nominal value for longer than 50 ms (overload) | → | Shut down pos. Charge Pump, Isolation Switch, Boost, Buck3, neg. Charge Pump controller (Buck1 and Buck2 keep working) → latched condition, only triggering UVLO enables the device again. |
7.3.5.6 Negative Charge-Pump Controller (V(GL)):
| When V(GL) < 40% of its nominal value | → | Shut down neg. Charge Pump, Isolation Switch, Boost, Buck3, pos. Charge Pump controller (Buck1 and Buck2 keep working) → latched condition, only triggering UVLO enables the device again. |
| When V(GL) < 80% of its nominal value for longer than 50 ms (overload) | → | Shut down neg. Charge Pump, Isolation Switch, Boost, Buck3, pos. Charge Pump controller (Buck1 and Buck2 keep working) → latched condition, only triggering UVLO enables the device again. |
Figure 12. Short-Circuit Levels Overview
7.4 Device Functional Modes
7.4.1 Boost Converter (V(AVDD))
The quasi-synchronous current mode boost converter operates with Pulse Width Modulation (PWM) with a fixed frequency of 750 kHz. For maximum design flexibility and stability with different external components, the converter uses external loop compensation by a simple RC circuit. The converter has an input-to-output switch at the output rail to disconnect its output.
7.4.1.1 Soft-Start
The boost converter is enabled by the EN-pin, the startup is done in two steps:
-
Input-to-output isolation switch soft-start
The isolation switch is turned on slowly in 10 ms -
Boost converter soft-start
When the isolation switch is fully turned on (after 10 ms) the boost converter starts switching and ramps up its output voltage V(AVDD) from VI to the programmed voltage value in 10 or 20 ms (programmable by I2C).
7.4.1.2 Compensation
The regulator loop can be compensated by adjusting the external RC circuit connected to the COMP pin. The COMP-pin is the output of the transconductance error amplifier. The compensation capacitor adjusts the low frequency gain and the resistor the high frequency gain. Lower output voltages require a higher gain and therefore a smaller compensation capacitor. A good start working for most applications is C(COMP) = 470 pF and R(COMP) = 75 kΩ. In case of a high noise level an additional 22-pF capacitor can be put between the COMP-pin and GND to filter the high frequency noise. The cut-off frequency can be calculated as follows:
7.4.1.3 Setting the Output Voltage V(AVDD)
The output voltage is programmable by I2C between 13.5 V and 19.8 V in 100 mV steps.
7.4.1.4 High Voltage Stress Mode (HVS)
By pulling the HVS-pin “high” an I2C programmable offset voltage is added to the set boost and buck 3 converters output voltage V(AVDD) and V(HAVDD). The offset voltages are programmable independently.
7.4.1.5 Programmable Current Limit
The current limit of typ. 5 A can be reduced by I2C programming in 400 mA steps down to 2.2 A to support smaller inductors with lower saturation current.
7.4.1.6 Design Procedure
The first step in the design procedure is to verify whether the maximum possible output current of the boost converter supports the specific application requirements.
- Converter Duty Cycle:
- Inductor ripple current:
- Maximum output current:
- Peak switch current:
SPACER
η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.9 as an estimation)
ƒs = Switching frequency (typ. 750 kHz)
L = Selected inductor value (typ. 6.8 µH)
ILIM_min: Minimum current limit
ISWPEAK = Peak switch current for the used output current (must be < ILIM_min = 4.25 A)
ΔIL = Inductor peak-to-peak ripple current
The peak switch current ISWPEAK is the current that the integrated switch, the inductor and the external Schottky diode have to be able to handle. The calculation must be done for the minimum input voltage where the peak switch current is the highest.
7.4.1.7 Inductor Selection
| Inductor value: | 4.7 µH ≤ L ≤ 10 µH | The higher the inductor value the lower the inductor current ripple and the output voltage ripple but the slower the transient response. |
| Saturation current: | ISAT ≥ ISWPEAK
or ISAT ≥ ILIM_max |
The inductor saturation current must be higher than the switch peak current for the max. peak output current or as a more conservative approach higher than the max. switch current limit. |
| DC resistance: | The lower the inductors resistance the lower the losses and the higher the efficiency. | |
| INDUCTANCE | SUPPLIER(1) | COMPONENT CODE | SIZE (L x W x H mm) | DCR Typ. (mΩ) | ISAT (A) |
|---|---|---|---|---|---|
| 6.8 µH | Sumida | CDRH105R | 10.5 x 10.3 x 5.1 | 14 | 5.4 |
| 6.8 µH | Sumida | CDRH10D43R | 10.8 x 10.5 x 4.5 | 20 | 7 |
| 10 µH | Sumida | CDRH10D43R | 10.8 x 10.5 x 4.5 | 26 | 5.2 |
| 6.8 µH | Chilisin | SCDS105R | 10.5 x 10.3 x 5.1 | 14 | 5.4 |
| 6.8 µH | Chilisin | SCDS104R | 10.5 x 10.3 x 4 | 21 | 5 |
| 10 µH | Chilisin | SCDS105R | 10.5 x 10.3 x 5.1 | 22 | 4.45 |
7.4.1.8 Rectifier Diode Selection
7.4.1.8.1 Diode Type
Schottky or Super Barrier Rectifier (SBR) for better efficiency
7.4.1.8.2 Forward Voltage
The lower the forward voltage VF the higher the efficiency and the lower the diode temperature.
7.4.1.8.3 Reverse Voltage
VR must be higher than the output voltage and should be higher than the OVP voltage 22.5 V
7.4.1.8.4 Thermal Characteristics
The diode must be able to handle the dissipated power of:
Table 1. Diodes
| VR / IAVG | VF Typ. at 25°C | COMPONENT CODE | RθJL | SIZE | SUPPLIER(1) |
|---|---|---|---|---|---|
| 30 V / 3 A | 0.39 V at 3 A | SBR3U30P1 | 5 °C/W | PowerDI® 123 | Diodes |
| 30 V / 3 A | 0.39 V at 3 A | SSM33LSPT | 18 °C/W | SMA-S | Chenmko |
| 40 V / 3 A | 0.38 V at 3 A | SSM34LAS | 18 °C/W | SMA-S | Chenmko |
| 40 V / 2 A | 0.5 V at 2 A | SSM24APT | 20 °C/W | SMA-S | Chenmko |
7.4.1.9 Output Capacitor Selection
For best output voltage filtering, low ESR ceramic capacitors are recommended. Four 10 µF (or two 22 µF) ceramic capacitors work for most applications. To improve the load transient response more capacitance can be added. Between the rectifier diode and the SWI-pin one 10 µF capacitor is required.
To calculate the output voltage ripple the following equations can be used:
| CAPACITOR | VOLTAGE RATING | TEMPERATURE CHARACTERISTICS | SUPPLIER(1) | COMPONENT CODE |
|---|---|---|---|---|
| 10 µF / 1206 | 25 V | X5R | Murata | GRM31CR61E106KA12 |
| 10 µF / 1206 | 25 V | X7R | Taiyo Yuden | TMK316AB7106KL |
7.4.2 Buck 1 Converter (V(IO))
The non-synchronous current mode buck 1 converter operates with Pulse Width Modulation (PWM) with a fixed frequency of 750 kHz. The converter features integrated soft-start, bootstrap and compensation to minimize external component and pin count.
The buck 1 converter operates in Discontinuous Conduction Mode (DCM) or Continuous Conduction Mode (CCM) depending on the load current. For low load currents the converter operates in DCM. In this mode the inductor current reaches 0 A when the switch is turned off. With increasing load current the inductor current finally does not reach 0 A anymore but is always positive and then the converter operates in CCM. The switch node waveforms for DCM and CCM operation are shown in Figure 23 and Figure 24. The ringing during DCM (at light load) is normal for this operating mode, it occurs because of parasitic capacitance in the PCB layout. Because there is very little energy contained in the ringing waveform it does not significantly affect EMI performance.
Minimum output current for DCM: M
For low load currents when the minimum on time is not sufficient, the buck 1 converter uses a skip mode to be able to regulate its output voltage V(IO). During the skip mode the converter switches for a few cycles to raise the output voltage then it stops switching until the output voltage falls below a given threshold and the converter starts switching again. Due to this behavior the output voltage ripple can be slightly higher during skip mode.
7.4.2.1 Soft-Start
The buck 1 converter is enabled with the undervoltage lockout (UVLO). It starts switching and ramps up its output voltage V(IO) linearly in 3 ms to the programmed voltage value.
7.4.2.2 Setting the Output Voltage V(IO)
The output voltage is programmable by I2C between 2.2 V and 3.7 V in 100 mV steps.
7.4.2.3 Design Procedure
The first step in the design procedure is to verify whether the maximum possible output current of the buck 1 converter supports the specific application requirements. Because the buck 2 converter is supplied by the buck 1 converter and the negative charge pump is driven from the buck 1 converter’s switch node the effective output current I(IO) is higher than the buck 1 output current alone.
- Converter Duty Cycle:
- Inductor ripple current:
- Maximum output current:
- Peak switch current:
- Effective output current:
spacer
η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.8 as an estimation)
ƒs = Switching frequency (typ. 750 kHz)
L = Selected inductor value (typ. 6.8 µH)
ILIM_min: Minimum current limit (3 A)
ISWPEAK = Peak switch current for the used output current (must be < ILIM_min = 3 A)
ΔIL = Inductor peak-to-peak ripple current
The peak switch current ISWPEAK is the current that the integrated switch, the inductor and the external Schottky diode have to be able to handle. The calculation must be done for the maximum input voltage where the peak switch current is the highest.
7.4.2.4 Inductor Selection
| Inductor value: | 4.7 µH ≤ L ≤ 10 µH | The higher the inductor value the lower the inductor current ripple and the output voltage ripple but the slower the transient response. |
| Saturation current: | ISAT ≥ ISWPEAK
or ISAT ≥ ILIM_max |
The inductor saturation current must be higher than the switch peak current for the max. peak output current or as a more conservative approach higher than the max. switch current limit. |
| DC resistance: | The lower the inductors resistance the lower the losses and the higher the efficiency. | |
| INDUCTANCE | SUPPLIER(1) | COMPONENT CODE | SIZE (L x W x H mm) | DCR Typ. (mΩ) | ISAT (A) |
|---|---|---|---|---|---|
| 6.8 µH | Sumida | CDRH8D43 | 8.3 x 8.3 x 4.5 | 20 | 4.4 |
| 10 µH | Sumida | CDRH8D43 | 8.3 x 8.3 x 4.5 | 29 | 4 |
| 6.8 µH | Chilisin | SCPS0740T | 7.5 x 7.8 x 4 | 28 | 3.9 |
7.4.2.5 Rectifier Diode Selection
7.4.2.5.1 Diode Type
Schottky or Super Barrier Rectifier (SBR) for better efficiency
7.4.2.5.2 Forward Voltage
The lower the forward voltage VF the higher the efficiency and the lower the diode temperature.
7.4.2.5.3 Reverse Voltage
VR must be higher than the output voltage
7.4.2.5.4 Forward Current
The average rectified forward current IAVG must be higher than IOUT × (1 – D)
7.4.2.5.5 Thermal Characteristics
The diode must be able to handle the dissipated power of:
Table 2. Diodes
| VR / IAVG | VF typ. at 25°C | COMPONENT CODE | RθJL | SIZE | SUPPLIER(1) |
|---|---|---|---|---|---|
| 30 V / 3 A | 0.39 V at 3 A | SBR3U30P1 | 5 °C/W | PowerDI® 123 | Diodes |
| 30 V / 3 A | 0.39 V at 3 A | SSM33LSPT | 18 °C/W | SMA-S | Chenmko |
| 40 V / 3 A | 0.38 V at 3 A | SSM34LAS | 18 °C/W | SMA-S | Chenmko |
| 40 V / 2 A | 0.5 V at 2 A | SSM24APT | 20 °C/W | SMA-S | Chenmko |
7.4.2.6 Output Capacitor Selection
For best output voltage filtering low ESR ceramic capacitors are recommended. Three 10 µF (or two 22 µF) ceramic capacitors work for most applications. To improve the load transient response more capacitance can be added.
To calculate the output voltage ripple the following equations can be used:
| CAPACITOR | VOLTAGE RATING | TEMPERATURE CHARACTERISTICS | SUPPLIER(1) | COMPONENT CODE |
|---|---|---|---|---|
| 10 µF / 1206 | 6.3 V | X5R | Murata | GRM219R60J106KE19 |
| 10 µF / 1206 | 6.3 V | X7R | Taiyo Yuden | JMK212AB7106KG |
7.4.3 BUCK 2 CONVERTER (V(CORE))
The synchronous current mode buck 2 converter operates with Pulse Frequency Modulation (PFM) with a fixed off-time and a typ. frequency of 1 MHz. The converter features integrated soft-start, bootstrap and compensation to minimize external component and pin count. It is supplied by the buck 1 converter’s output.
If not needed the buck 2 converter can be disabled by I2C.
7.4.3.1 Soft-Start
The buck 2 converter is enabled when the buck 1 converter is in regulation. It starts switching and ramps up its output voltage V(CORE) linearly in 3ms to the programmed voltage value.
7.4.3.2 Setting the Output Voltage V(CORE)
The output voltage is programmable by I2C between 0.8 V and 3.3 V in 100 mV steps.
7.4.3.3 Design Procedure
The first step in the design procedure is to verify whether the maximum possible output current of the buck 2 converter supports the specific application requirements.
- Switching frequency: M
- Converter Duty Cycle: M
- Inductor ripple current: M
- Maximum output current: M
- Peak switch current: M
spacer
η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.8 as an estimation)
L = Selected inductor value (typ. 6.8 µH)
ILIM_min: Minimum current limit (2.5A)
ISWPEAK = Peak switch current for the used output current (must be < ILIM_min = 2.5 A)
ΔIL = Inductor peak-to-peak ripple current
The peak switch current ISWPEAK is the current that the switch and the inductor have to be able to handle.
7.4.3.4 Inductor Selection
| Inductor value: | 4.7µH ≤ L ≤ 10µH | The higher the inductor value the lower the inductor current ripple and the output voltage ripple but the slower the transient response. |
| Saturation current: | ISAT ≥ ISWPEAK
or ISAT ≥ ILIM_max |
The inductor saturation current must be higher than the switch peak current for the max. peak output current or as a more conservative approach higher than the max. switch current limit. |
| DC resistance: | The lower the inductors resistance the lower the losses and the higher the efficiency. | |
| INDUCTANCE | SUPPLIER(1) | COMPONENT CODE | SIZE (L x W x H mm) | DCR typ. (mΩ) | ISAT (A) |
|---|---|---|---|---|---|
| 4.7 µH | Sumida | CDRH5D28R/HP | 6.2 x 6.2 x 3 | 35 | 3.7 |
| 6.8 µH | Sumida | CDRH5D28R/HP | 6.2 x 6.2 x 3 | 49 | 3.1 |
| 4.7 µH | Chilisin | SCPS0725T | 7.8 x 7.7 x 2.5 | 40 | 4 |
| 6.8 µH | Chilisin | SCPS0725T | 7.8 x 7.7 x 2.5 | 66 | 3.5 |
| 4.7 µH | Chilisin | LVS606028 | 6.2 x 6.2 x 2.2 | 38 | 3.7 |
| 6.8 µH | Chilisin | LVS606028 | 6.2 x 6.2 x 2.2 | 50 | 3.1 |
| 4.7 µH | Mag Layers | MSCDRI-7025AL | 8 x 8 x 2.5 | 45 | 3.5 |
| 6.8 µH | Mag Layers | MSCDRI-7025AL | 8 x 8 x 2.5 | 63 | 3.1 |
7.4.3.5 Output Capacitor Selection
For best output voltage filtering low ESR ceramic capacitors are recommended. Three 10 µF (or one 22 µF) ceramic capacitors work for most applications. To improve the load transient response more capacitance can be added.
To calculate the output voltage ripple the following equations can be used:
| CAPACITOR | VOLTAGE RATING | TEMPERATURE CHARACTERISTICS | SUPPLIER(1) | COMPONENT CODE |
|---|---|---|---|---|
| 10 µF / 1206 | 6.3 V | X5R | Murata | GRM219R60J106KE19 |
| 10 µF / 1206 | 6.3 V | X7R | Taiyo Yuden | JMK212AB7106KG |
7.4.4 Buck 3 Converter (V(HAVDD))
The synchronous current mode buck 3 converter operates with Pulse Frequency Modulation (PFM) with a fixed off-time and a typ. frequency of 1 MHz. The converter features integrated soft-start, bootstrap and compensation to minimize external component and pin count.
If not needed the buck 3 converter can be disabled by I2C.
7.4.4.1 Soft-Start
The buck 3 converter is enabled together with the boost converter. It starts switching and ramps up its output voltage V(HAVDD) to the programmed voltage value tracking the boost converters output voltage V(AVDD).
7.4.4.2 Setting the Output Voltage V(HAVDD)
The output voltage is programmable by I2C between 4.8 V and 11.1 V in 100 mV steps.
7.4.4.3 High Voltage Stress Mode (HVS)
By pulling the HVS-pin “high” an I2C programmable offset voltage is added to the set boost and buck 3 converters output voltage V(AVDD) and V(HAVDD). The offset voltages are programmable independently.
7.4.4.4 Design Procedure
The first step in the design procedure is to verify whether the maximum possible output current of the buck 3 converter supports the specific application requirements.
- Switching frequency: M
- Converter Duty Cycle: M
- Inductor ripple current: M
- Maximum output current: M
- Peak switch current: M
spacer
η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.8 as an estimation)
fS: Switching frequency (typ. 1 MHz)
L = Selected inductor value (typ. 6.8 µH)
ILIM_min: Minimum current limit (1.7 A)
ISWPEAK = Peak switch current for the used output current (must be < ILIM_min = 1.7 A)
ΔIL = Inductor peak-to-peak ripple current
The peak switch current ISWPEAK is the current that the switch and the inductor have to be able to handle.
7.4.4.5 Inductor Selection
| Inductor value: | 4.7 µH ≤ L ≤ 10 µH | The higher the inductor value the lower the inductor current ripple and the output voltage ripple but the slower the transient response. |
| Saturation current: | ISAT ≥ ISWPEAK
or ISAT ≥ ILIM_max |
The inductor saturation current must be higher than the switch peak current for the max. peak output current or as a more conservative approach higher than the max. switch current limit. |
| DC resistance: | The lower the inductors resistance the lower the losses and the higher the efficiency. | |
| INDUCTANCE | SUPPLIER(1) | COMPONENT CODE | SIZE (L x W x H mm) | DCR typ. (mΩ) | ISAT (A) |
|---|---|---|---|---|---|
| 4.7 µH | Chilisin | SCDS6D28T | 7 x 7 x 3 | 25 | 2.5 |
| 6.8 µH | Chilisin | SCDS6D28T | 7 x 7 x 3 | 40 | 2.1 |
| 4.7 µH | Chilisin | SCPS0725T | 7.8 x 7.7 x 2.5 | 40 | 4 |
| 6.8 µH | Chilisin | SCPS0725T | 7.8 x 7.7 x 2.5 | 66 | 3.5 |
| 4.7 µH | Chilisin | LVS404018 | 4.2 x 4.2 x 2 | 90 | 2 |
| 6.8 µH | Chilisin | LVS404018 | 4.2 x 4.2 x 2 | 110 | 1.6 |
| 4.7 µH | Mag Layers | MSCDRI-7025AL | 8 x 8 x 2.5 | 45 | 3.5 |
| 6.8 µH | Mag Layers | MSCDRI-7025AL | 8 x 8 x 2.5 | 63 | 3.1 |
7.4.4.6 Output Capacitor Selection
For best output voltage filtering low ESR ceramic capacitors are recommended. One 10 µF ceramic capacitor works for most applications. To improve the load transient response more capacitance can be added.
To calculate the output voltage ripple the following equations can be used:
| CAPACITOR | VOLTAGE RATING | TEMPERATURE CHARACTERISTICS | SUPPLIER(1) | COMPONENT CODE |
|---|---|---|---|---|
| 10 µF / 1206 | 16 V | X5R | Murata | GRM31CR61C106KA88 |
| 10 µF / 1206 | 16 V | X7R | Taiyo Yuden | EMK316AB7106KL |
7.4.5 Positive Charge Pump Controller (V(GH)) with Temperature Compensation
The positive charge pump is driven from the boost converter’s switch node and regulated by controlling the current through an external PNP transistor. The controller is optimized for transistors with a DC gain (hFE) between 100 and 300, a base drive current up to 5 mA is supported. A temperature compensation for its output voltage V(GH) is implemented and the levels of the output voltages are programmed by I2C.
The positive charge pump and the temperature compensation function can be disabled by I2C separately.
7.4.5.1 Soft-Start
The positive charge pump controller is enabled when the boost converter is in regulation. The output voltage V(GH) ramps up to the programmed voltage in typ. 1.5 ms.
7.4.5.2 Setting the Output Voltage V(GH)
The low voltage V(GH_LOW) at high temperature is programmed directly by I2C from 20 V to 35 V in 1 V steps, the high voltage V(GH_HIGH) at low temperature is programmed with a positive offset voltage of 1 V steps relative to V(GH_LOW). An external NTC thermistor with a resistor network (RP and RL) sets the temperatures when V(GH_LOW) (VNTC ≤ 1 V, hot) and V(GH_HIGH) (VNTC ≥ 2 V, cold) are reached. To achieve a linear curve between V(GH_LOW) and V(GH_HIGH) a suitable linearalization resistor parallel to the NTC must be used.
 |
||
| RT0 is the resistance at an absolute temperature T0 in Kelvin (normally 25°C) T is the temperature in Kelvin (°C + 273.15 K/°C) B is a material constant provided by the NTC supplier |
 |
|
| VL: Internal supply voltage VL = 5 V |  |
|
| RNTC(THOT): NTC resistance hot | ||
| RNTC(TCOLD): NTC resistance cold | ||
7.4.5.3 Design Procedure
- Supported max. output voltage
- Diode selection
- Transistor selection
- Base-Emitter resistor selection
- Flying capacitor selection
- Switch node resistor selection
The maximum possible output voltage is calculated as follows:
Doubler Mode: 
Tripler Mode: 
VF: Diode forward voltage
R: Switch node resistor
VINPUT: Transistor emitter voltage
D: Boost duty cycle
C: Flying capacitor value
fS: Boost switching frequency (750kHz)
VQ: Collector-emitter saturation voltage
Diode type: No specific type required
Forward voltage: The lower the forward voltage VF the higher the maximum output voltage
Reverse voltage: VR must be higher than the switching voltage applied at the flying capacitor
Forward current: The average forward current IAVG must be higher than the output current IOUT
Thermal characteristics: The diode must be able to handle the dissipated power of PD = VF × IOUT
Peak currents of up to some amps through the diodes can occur during start-up for a few cycles. This condition lasts for <1ms and can be tolerated by many diodes whose repetitive peak current rating is much lower.
| VR / IAVG | VF typ. at 25°C | COMPONENT CODE | RθJA | SIZE | SUPPLIER(1) |
|---|---|---|---|---|---|
| 85 V / 150 mA | 1.1 V at 150 mA | BAV99TPT | SOT-416 | Chenmko | |
| 75 V / 300 mA | 1 V at 150 mA | BAV99W | 625 °C/W | SOT-323 | Diodes |
| 75 V / 215 mA | 1.1 V at 150 mA | BAV99BDWPT | 625 °C/W | SOT-363 | Chenmko |
| 75 V / 300 mA | 1 V at 150 mA | BAV99BRW | 625 ºC/W | SOT-363 | Diodes |
| 75 V / 300 mA | 1 V at 150 mA | BAV99T | 833 ºC/W | SOT-523 | Diodes |
| 30 V / 1 A | 0.47 V at 1 A | CH511H-30PT | 625 ºC/W | SOT-323 | Chenmko |
| 40 V / 200 mA | 0.9 V at 200 mA | BAS40W-04 | 625 ºC/W | SOT-323 | Diodes |
| 40 V / 200 mA | 0.9 V at 200 mA | BAS40-04T | 833 ºC/W | SOT-523 | Diodes |
| 30 V / 200 mA | 0.65 V at 200 mA | BAT54SW | 625 ºC/W | SOT-323 | Diodes |
| 30 V / 200 mA | 0.65 V at 200 mA | BAT54ST | 833 ºC/W | SOT-523 | Diodes |
| 75 V / 300 mA | 1 V at 200 mA | MMBD7000 | 357 ºC/W | SOT-23 | Diodes |
DC gain (hFE): At least 35 when the transistors collector current is equal to the output current, for good performance 75 to 200 is recommended
Collector-Emitter voltage: VCEO must be at least the input voltage (Emitter voltage) + switching voltage VAVDD
DC Collector current: Must be higher than the output current IOUT / (1 – boost duty cycle)
Thermal characteristics: The transistor must be able to handle the dissipated power of:
Doubler Mode: 
Tripler Mode: 
VINPUT: Input voltage
VF: Diode forward voltage
IGH: Mean output current
D: Boost duty cycle
R: Switch node resistor
C: Flying capacitor value
fS: Boost switching frequency (750kHz)
The total power dissipation of the chosen package is specified with a very good thermal designed PCB. The specified max. power dissipation can only be dissipated if the cooling area at the PCB is big enough. The total area should be at least 5 cm2 it can be spread over different layers when using many vias.
| VCEO / IC | hFE min…max. | VCEsat | COMPONENT CODE | Ptot | SIZE | SUPPLIER(1) |
|---|---|---|---|---|---|---|
| –60 V / –600 mA | 100…300 at –150 mA | –150 mV | CHT2907XPT | 1.2 W | SOT-89 | Chenmko |
| –40 V / –200 mA | 60…300 at –50 mA | –200 mV | CH3906XPT | 1.2 W | SOT-89 | Chenmko |
| –50 V /–2 A | 70…240 at –500 mA | –150 mV | KTA1666 | 1 W | SOT-89 | KEC |
| –60 V / –1 A | 50…200 at –500 mA | –300 mV | KTA1668 | 1 W | SOT-89 | KEC |
| –60 V / –600 mA | 100…300 at –150 mA | –150 mV | PZT2907AT1 | 1.5 W | SOT-223 | ON Semi |
A 100-kΩ base-emitter resistor is required to ensure proper operation. It is needed to ensure that the transistor can be turned off completely. Too low resistor value reduce the maximum base drive current.
A flying capacitor of 470 nF is appropriate for most applications. Larger capacitances have a smaller voltage drop ?V at the end of each switching cycle and support therefore higher output voltages and currents. The voltage rating must be at least the switching voltage V(AVDD).
| C: Flying capacitor value |  |
|
| fS: Boost switching frequency (750kHz) |
| CAPACITOR | VOLTAGE RATING | TEMPERATURE CHARACTERISTICS | SUPPLIER(1) | COMPONENT CODE |
|---|---|---|---|---|
| 470 nF / 0603 | 25 V | X7R | Murata | GRM188R71E474KA12 |
| 470 nF / 0603 | 25 V | X5R | Taiyo Yuden | TMK107BJ474KA |
For less boost converter disturbance and therefore lower boost output voltage ripple ?V(AVDD) and lower diode current spikes a resistor should be added in the switching path. The higher the resistance the lower the disturbances and the peak currents but also the lower the maximum output current and the higher the resistors power dissipation PR. A 1 Ω to 2.2 Ω resistor is appropriate for most applications.
7.4.5.4 Output Capacitor Selection
For best output voltage filtering low ESR ceramic capacitors are recommended. One 4.7 µF ceramic capacitor works for most applications. To improve the load transient response more capacitance can be added.
| CAPACITOR | VOLTAGE RATING | TEMPERATURE CHARACTERISTICS | SUPPLIER(1) | COMPONENT CODE |
|---|---|---|---|---|
| 4.7 µF / 1206 | 50 V | X7R | Murata | GRM31CR71H475KA12 |
| 4.7 µF / 1206 | 50 V | X5R | Taiyo Yuden | UMK316BJ475KL |
7.4.6 Negative Charge Pump Controller (V(GL))
The negative charge pump usually is driven from the buck 1 converter’s switch node but can also be connected to the boost converter’s switch node and regulated by controlling the current through an external NPN transistor. The controller is optimized for transistors with a DC gain (hFE) between 100 and 300, a base drive current up to 5 mA is supported.
The negative charge pump can be disabled by I2C.
TPS65177A:
When V(GL) is driven by the boost switch pin (SW) the EN-pin should be connected to VI, otherwise V(GL) detects a short when EN is pulled low as the V(GL) voltage collapses. V(GL) collapses because the supporting switch node (SW) stops switching and the device partially shuts down as described in the Short-Circuit and Overload Protection section. The device is in a latched state and only a power cycle can restart the V(AVDD), V(HAVDD), V(GH) and V(GL) rail.
7.4.6.1 Soft-Start
The negative charge pump controller is enabled when the buck 2 converter is in regulation. The output voltage V(GL) ramps up to the programmed voltage in typ. 1.5 ms.
7.4.6.2 Setting the Output Voltage V(GL)
The output voltage is programmable by I2C between –14.5 V and –5.5 V in 600 mV steps.
7.4.6.3 Design Procedure
- Supported max. output voltage
- Diode selection
- Transistor selection
- Base-Emitter resistor selection
- Flying capacitor selection
- Switch node resistor selection
The maximum possible negative output voltage is calculated as follows:
Using buck 1 converter’s switch node:
Inverter: 
VINPUT: Transistor emitter node voltage
VF: Diode forward voltage
R: Switch node resistor
D: Buck duty cycle
C: Flying capacitor value
fS: Boost and Buck1 switching frequency (750kHz)
VQ: Collector-emitter saturation voltage
Using boost converter’s switch node:
Inverter: 
Diode type: No specific type required
Forward voltage: The lower the forward voltage VF the higher the maximum output voltage
Reverse voltage: VR must be higher than the switching voltage applied at the flying capacitor VIN or VAVDD
Forward current: The average forward current IAVG must be higher than the output current IOUT
Thermal characteristics: The diode must be able to handle the dissipated power of PD = VF × IOUT
Peak currents of up to some amps through the diodes can occur during start-up for a few cycles. This condition lasts for < 1 ms and can be tolerated by many diodes whose repetitive peak current rating is much lower.
| VR / IAVG | VF typ. at 25°C | COMPONENT CODE | RθJA | SIZE | SUPPLIER(1) |
|---|---|---|---|---|---|
| 85 V / 150 mA | 1.1 V at 150 mA | BAV99TPT | SOT-416 | Chenmko | |
| 75 V / 300 mA | 1 V at 150 mA | BAV99W | 625 °C/W | SOT-323 | Diodes |
| 75 V / 215 mA | 1.1 V at 150 mA | BAV99BDWPT | 625 °C/W | SOT-363 | Chenmko |
| 75 V / 300 mA | 1 V at 150 mA | BAV99BRW | 625 ºC/W | SOT-363 | Diodes |
| 75 V / 300 mA | 1 V at 150 mA | BAV99T | 833 ºC/W | SOT-523 | Diodes |
| 30 V / 1 A | 0.47 V at 1 A | CH511H-30PT | 625 ºC/W | SOT-323 | Chenmko |
| 40 V / 200 mA | 0.9 V at 200 mA | BAS40W-04 | 625 ºC/W | SOT-323 | Diodes |
| 40 V / 200 mA | 0.9 V at 200 mA | BAS40-04T | 833 ºC/W | SOT-523 | Diodes |
| 30 V / 200 mA | 0.65 V at 200 mA | BAT54SW | 625 ºC/W | SOT-323 | Diodes |
| 30 V / 200 mA | 0.65 V at 200 mA | BAT54ST | 833 ºC/W | SOT-523 | Diodes |
| 75 V / 300 mA | 1 V at 200 mA | MMBD7000 | 357 ºC/W | SOT-23 | Diodes |
DC gain (hFE): At least 35 when the transistors collector current is equal to the output current, for good performance 75 to 200 is recommended
Collector-Emitter voltage: VCEO must be at least the input voltage (Emitter voltage) + switching voltage VI or V(AVDD)
DC Collector current: Must be higher than the output current IOUT / (1 – buck duty cycle) or IOUT / boost duty cycle
Thermal characteristics: The transistor must be able to handle the dissipated power of:
Using buck 1 converter’s switch node:
Inverter: 
VF: Diode forward voltage
VINPUT: Input voltage
IGL: Mean output current
R: Switch node resistor
D: Buck duty cycle
C: Flying capacitor value
fS: Boost and Buck 1 switching frequency (750kHz)
Using boost converter's switch node:
Inverter: 
The total power dissipation of the chosen package is specified with a very good thermal designed PCB. The specified max. power dissipation can only be dissipated if the cooling area at the PCB is big enough. The total area should be at least 5 cm2 it can be spread over different layers when using many vias.
| VCEO / IC | hFE min…max. | VCEsat | COMPONENT CODE | Ptot | SIZE | SUPPLIER(1) |
|---|---|---|---|---|---|---|
| 40 V / 600 mA | 100…300 at 150 mA | 150 mV | CHT2222XPT | 1.2 W | SOT-89 | Chenmko |
| 40 V / 200 mA | 60…300 at 50 mA | 100 mV | CH3904XPT | 1.2 W | SOT-89 | Chenmko |
| 80 V / 400 mA | 50…240 at 200 mA | 100 mV | KTC4374 | 1 W | SOT-89 | KEC |
| 30 V / 1.5 A | 100…320at 500 mA | 150 mV | KTC4375 | 1 W | SOT-89 | KEC |
| 30 V / 800 mA | 50…320 at 500 mA | 150 mV | KTC4376 | 1 W | SOT-89 | KEC |
| 40 V / 600 mA | 40…300 at 500 mA | 500 mV | PZT2222AT1 | 1.5 W | SOT-223 | ON Semi |
| 40 V / 200 mA | 60…300 at 50 mA | 200 mV | PZT3904T1G | 1.5 W | SOT-223 | ON Semi |
A 100 kΩ base-emitter (DRVN-pin to GND) resistor is integrated to ensure proper operation there is no external resistor needed. It is needed to ensure that the transistor can be turned off completely.
A flying capacitor of 470 nF is appropriate for most applications. Larger capacitances have a smaller voltage drop ?V at the end of each switching cycle and support therefore higher output voltages and currents. The voltage rating must be at least the switching voltage VI (using buck 1 switch) or V(AVDD) (using boost switch).
| C: Flying capacitor value fS: Buck 1 or Boost switching frequency (750 kHz) |
 |
| CAPACITOR | VOLTAGE RATING | TEMPERATURE CHARACTERISTICS | SUPPLIER(1) | COMPONENT CODE |
|---|---|---|---|---|
| 470 nF / 0603 | 25 V | X7R | Murata | GRM188R71E474KA12 |
| 470 nF / 0603 | 25 V | X5R | Taiyo Yuden | TMK107BJ474KA |
For less buck 1 or boost converter disturbance and therefore lower buck 1 or boost output voltage ripple ?V(IO) or ?V(AVDD) and lower diode current spikes a resistor should be added in the switching path. The higher the resistance the lower the disturbances and the peak currents but also the lower the maximum output current and the higher the resistors power dissipation. A 1 Ω to 2.2 Ω resistor is appropriate for most applications
7.4.6.4 Output Capacitor Selection
For best output voltage filtering low ESR ceramic capacitors are recommended. One 4.7µF ceramic capacitor works for most applications. To improve the load transient response more capacitance can be added.
| CAPACITOR | VOLTAGE RATING | TEMPERATURE CHARACTERISTICS | SUPPLIER(1) | COMPONENT CODE |
|---|---|---|---|---|
| 4.7 µF / 1206 | 16 V | X5R | Murata | GRM21BR61C475KA88 |
| 4.7 µF / 1206 | 16 V | X7R | Taiyo Yuden | EMK212B7475KG |
7.5 Gate Pulse Modulation (V(GHM))
The Gate Pulse Modulation is controlled by the CTRL-pin, except during start-up and shut-down. During start-up V(GHM) is kept at low state (V(GHM) = V(RE)) until Power Good of the positive charge pump V(GH) is reached, at shut-down V(GHM) follows V(GH) (V(GHM) = V(GH)).
If not needed the Gate Pulse Modulation can be disabled by I2C.
CTRL = ‘high’ → V(GHM) = V(GH)
CTRL = ‘low’ → V(GHM) = V(RE) (discharges through RE resistor)
The slope at which V(GHM) discharges is set by the external resistor connected to the RE-pin, the internal MOSFET RDS(ON) (typ. 3 Ω) and the gate line capacitance connected to the VGHM-pin. The RE resistor must be connected to GND and it must also be able to handle the power dissipation.
A Gate Pulse Modulation limit voltage can be set by I2C programming. When the limit voltage is reached the discharging of VGHM through RE is stopped and the VGHM output is high impedance until CTRL goes “high” again, see Figure 13.
Figure 13. Gate Pulse Modulation
7.6 Programming
7.6.1 I2C Serial Interface Description
The TPS65177/A communicates through an industry standard 2-wire I2C interface to receive data in slave mode. The I2C serial interface was developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is among other things responsible for generating the SCL signal and the slave device address to communicate with a certain device. A slave device receives and/or transmits data on the bus under control of the master device. A START condition send by the master initiates a new data transfer to the slave devices. Transitioning SDA from high to low while SCL remains high generates a START condition. A STOP condition ends a data transfer to the selected slave device. Transitioning SDA from low to high while SCL remains high generates a STOP condition (see Figure 14).
Figure 14. START and STOP Conditions
The TPS65177/A works as a slave and supports the standard mode (100 kbps) and fast mode (400 kbps) data transfer mode, as defined in the I2C-Bus specification. The data transfer protocol for standard and fast mode is exactly the same. The TPS65177/A supports 7-bit addressing. The device 7-bit address is defined as ‘010000X’ (see Figure 15) where the bit X can be selected depending on the address pin configuration of A0 (“high” = 1, “low” = 0). The LSB enables the write or read function (“high” = read, “low” = write).
Figure 15. TPS65177/A Slave Address Byte
The master generates the SCL pulses, transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that the data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 16). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an Acknowledge, ACK, (see Figure 17) by pulling the SDA line low during the entire high period of the SCL cycle. Upon detecting this Acknowledge, the master knows that communication link with a slave has been established.
Figure 16. Bit Transfer on the Serial Interface
Figure 17. Acknowledge on the I2C Bus
The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data from the slave (R/W bit = 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To terminate the data transfer, the master generates the STOP condition by pulling the SDA line from low to high while the SCL line is high (see Figure 18). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released and they wait for a START condition followed by a matching slave address.
Figure 18. I2C Bus Protocol
Attempting to read data from register addresses not listed in the following section will result in 00h being read out.
7.6.2 Memory Description
A non-volatile EEPROM containing the initial values of the DACs and a volatile memory containing the DACs settings is implemented in the TPS65177/A. The non-volatile memory is called the Initial Value Register (IVR) and the volatile memory is called DAC Register (DR). The non-volatile IVR and the volatile DR are accessed by the same address. A Control Register (CR) is implemented to select if the IVR or the DR is addressed.
7.6.3 Read / Write Description
To read the volatile memory (DR) data the LSB (EE/DR) of the Control Register (CR) must be set to 0, to read the non-volatile EEPROM (IVR) data the LSB of the Control Register (CR) must be set to 1, then the data of the selected memory can be read.
To write data into the non-volatile EEPROM (IVR) all data registers (00h ~ 0Ch) must be programmed first and then the MSB (WED) of the Control Register (CR) must be set to 1. A dead time of 50ms is initiated during which all the register data (00h ~ 0Ch) is stored into the non-volatile EEPROM. It is not possible to write single DAC register data to the EEPROM. There should be not data flow at the I2C bus during that time because the I2C interface of the TPS65177/A is momentarily not responding. When the 50ms have passed the WED bit is automatically reset to 0.
7.6.4 Write Operation
7.6.4.1 Write Single Byte to the DAC Register (DR):
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send DAC register address (e.g. 01h, address of VAVDD)
TPS65177/A will Acknowledge this byte - Send the data byte to be written to the DAC register
TPS65177/A will Acknowledge this byte - Master sends STOP condition on the bus
Example: Writing 0Fh (15 V) to the DAC address 01h (Boost converter V(AVDD))
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | SLAVE ACK | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | SLAVE ACK | STOP |
7.6.4.2 Write Multiple Bytes to the DAC Register (DR):
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send DAC register address (e.g. 01h, address of VAVDD)
TPS65177/A will Acknowledge this byte - Send the data byte to be written to the DAC register
TPS65177/A will Acknowledge this byte - Master continues sending data bytes to be written to the DA registers
(DAC register address pointer will automatically increase) - Master sends STOP condition on the bus
Example: Writing 0Fh, 05h, 00h to the DAC addresses 01h, 02h, 03h (V(AVDD), HVS, Current limit)
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | SLAVE ACK | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | SLAVE ACK |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | SLAVE ACK | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | STOP | ||||||||||
7.6.4.3 Write All DAC Register (DR) Data to EEPROM (EE):
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send Control register (CR) address of FFh
TPS65177/A will Acknowledge this byte - Send 1xxxxxxx to enable data copy from DAC registers (DR) to EEPROM (EE)
TPS65177/A will Acknowledge this byte - Master sends STOP condition on the bus
Example: Writing all DAC registers data to the EEPROM
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | SLAVE ACK |
1 | x | x | x | x | x | x | x | SLAVE ACK |
STOP |
7.6.5 READ OPERATION
7.6.5.1 Read single data from DAC register (DR):
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send Control register (CR) address of FFh
TPS65177/A will Acknowledge this byte - Send data byte of 00h (EE/ DR bit) to specify that the data is read from the DAC register
TPS65177/A will Acknowledge this byte - Master sends STOP condition on the bus
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send desired DAC register address to be read (00h~0Ch or FEh)
TPS65177/A will Acknowledge this byte - Master re-sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = High
TPS65177/A will Acknowledge this byte - Read data from DAC register
Master will not-Acknowledge this byte - Master sends STOP condition on the bus
Example: Reading data from the DAC register (DR) address 01h (V(AVDD))
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | SLAVE ACK |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SLAVE ACK |
STOP |
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | SLAVE ACK |
||||||||||
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 1 | SLAVE ACK |
D | D | D | D | D | D | D | D | MASTER N-ACK |
STOP | |||||||||
7.6.5.2 Read Multiple Data from DAC Register (DR):
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send Control register (CR) address of FFh
TPS65177/A will Acknowledge this byte - Send data byte of 00h (EE/ DR bit) to specify that the data is read from the DAC register
TPS65177/A will Acknowledge this byte - Master sends STOP condition on the bus
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send desired DAC register address to be read (00h~0Ch or FEh)
TPS65177/A will Acknowledge this byte - Master re-sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = High
TPS65177/A will Acknowledge this byte - Continue read data from the DAC register, the address pointer will increase automatically
Master will not-Acknowledge this byte - Master will not-acknowledge (N-ACK) after received the last reading data
- Master sends STOP condition on the bus
Writing 0Fh, 05h, 00h to the DAC addresses 01h, 02h, 03h (V(AVDD), HVS, Current limit)
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | SLAVE ACK |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SLAVE ACK |
STOP |
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | SLAVE ACK |
||||||||||
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 1 | SLAVE ACK |
D | D | D | D | D | D | D | D | MASTER ACK |
D | D | D | D | D | D | D | D | MASTER ACK | |
| D | D | D | D | D | D | D | D | MASTER N-ACK |
STOP | |||||||||||||||||||
7.6.5.3 Read Single Data to EEPROM (EE):
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send Control register (CR) address of FFh
TPS65177/A will Acknowledge this byte - Send data byte of 00h (EE/ DR bit) to specify that the data is read from the EEPROM
TPS65177/A will Acknowledge this byte - Master sends STOP condition on the bus
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send desired EEPROM register address to be read (00h~0Ch or FEh)
TPS65177/A will Acknowledge this byte - Master re-sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = High
TPS65177/A will Acknowledge this byte - Read data from EEPROM
Master will not-Acknowledge this byte - Master sends STOP condition on the bus
Example: Reading data from the EEPROM (EE) addresses 01h, 02h, 03h (V(AVDD), HVS, Current limit)
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | SLAVE ACK |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | SLAVE ACK |
STOP |
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | SLAVE ACK |
||||||||||
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK |
D | D | D | D | D | D | D | D | MASTER N-ACK |
STOP | |||||||||
7.6.5.4 Read Multiple Data to EEPROM (EE):
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send Control register (CR) address of FFh
TPS65177/A will Acknowledge this byte - Send data byte of 00h (EE/ DR bit) to specify that the data is read from the EEPROM
TPS65177/A will Acknowledge this byte - Master sends STOP condition on the bus
- Master sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = Low
TPS65177/A will Acknowledge this byte - Send desired EEPROM register address to be read (00h~0Ch or FEh)
TPS65177/A will Acknowledge this byte - Master re-sends START condition on the bus
- Master sends the TPS65177/A address 010000A0 and R/W bit = High
TPS65177/A will Acknowledge this byte - Continue read data from the EEPROM, the address pointer will increase automatically
Master will not-Acknowledge this byte - Master will not-acknowledge (N-ACK) after received the last reading data
- Master sends STOP condition on the bus
Example: Reading data from the EEPROM (EE) addresses 01h, 02h, 03h (V(AVDD), HVS, Current limit)
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | SLAVE ACK |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | SLAVE ACK |
STOP |
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 0 | SLAVE ACK |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | SLAVE ACK |
||||||||||
| START | 0 | 1 | 0 | 0 | 0 | 0 | A0 | 1 | SLAVE ACK |
D | D | D | D | D | D | D | D | MASTER N-ACK |
D | D | D | D | D | D | D | D | MASTER ACK | |
| D | D | D | D | D | D | D | D | MASTER N-ACK |
STOP | |||||||||||||||||||
7.6.6 Write Single Data to DAC:
7.6.7 Write Multiple Data to DAC (Auto Increment Address):
7.6.8 Write all DAC Data to EEPROM:
7.6.9 Read Single Data From DAC / EEPROM:
7.6.10 Read Multiple Data fFom DAC / EEPROM (Auto Increment Address):
7.7 Register Map
7.7.1 Registers and DAC Settings
Table 3. Device address with A0 selection pin (A0 = 0 or 1)
| MSB | TPS65177/A Address | LSB | |||||
|---|---|---|---|---|---|---|---|
| 0 | 1 | 0 | 0 | 0 | 0 | A0 | R/W |
Table 4. Control Register FFh (Factory value 00h)
| MSB | Address FFh | LSB | |||||
|---|---|---|---|---|---|---|---|
| WED (Write EEPROM Data) |
Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | EE/ DR
(Read EEPROM or DR) |
Table 5. Register Map
| Register | Name | Address | Factory value | Bit count | Steps count |
|---|---|---|---|---|---|
| Cannel | Channel Disable | 00h | 00h | 6 | 64 |
| Boost | Output voltage V(AVDD) | 01h | 0Fh | 6 | 64 |
| HVS offset | 02h | 05h | 4 | 16 | |
| Current Limit | 03h | 00h | 3 | 8 | |
| Soft-start time | 04h | 00h | 1 | 2 | |
| Buck 1 | Output voltage V(IO) | 05h | 03h | 4 | 16 |
| Buck 2 | Output voltage V(CORE) | 06h | 02h | 5 | 32 |
| Buck 3 | Output voltage V(HAVDD) | 07h | 1Bh | 6 | 64 |
| Pos. CP | Output voltage V(GH_L) | 08h | 08h | 4 | 16 |
| V(GH_L) to V(GH_H) offset voltage V(GH_OFS) | 09h | 04h | 4 | 16 | |
| GPM | GPM limit voltage | 0Ah | 00h | 2 | 4 |
| Neg. CP | Output voltage V(GL) | 0Bh | 04h | 4 | 16 |
| Buck 3 | HVS offset | 0Ch | 00h | 4 | 16 |
| Memory | Memory write remain time | FEh | Fh | 4 | 16 |
| Control | Control register | FFh | 00h | 8 | 256 |
7.7.1.1 Channel Register (with factory value) – 00h (00h)
| MSB | Address 00h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | 0 | 0 | 0 | 0 | 0 | 0 |
| MSB | Address 00h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | V(CORE) | V(HAVDD) | V(GH) | V(GL) | GPM | NTC |
| Enable: 0 | Enable: 0 | Enable: 0 | Enable: 0 | Enable: 0 | Enable: 0 | ||
| Disable:1 | Disable:1 | Disable:1 | Disable:1 | Disable:1 | Disable:1 | ||
7.7.1.2 Boost Output Voltage V(AVDD) Register (with factory value) – 01h (0Fh)
| MSB | Address 01h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | 0 | 0 | 1 | 1 | 1 | 1 |
| DAC Value | V(AVDD) | DAC Value | V(AVDD) | DAC Value | V(AVDD) | DAC Value | V(AVDD) |
|---|---|---|---|---|---|---|---|
| 00h | 13.5 V | 10h | 15.1 V | 20h | 16.7 V | 30h | 18.3 V |
| 01h | 13.6 V | 11h | 15.2 V | 21h | 16.8 V | 31h | 18.4 V |
| 02h | 13.7 V | 12h | 15.3 V | 22h | 16.9 V | 32h | 18.5 V |
| 03h | 13.8 V | 13h | 15.4 V | 23h | 17.0 V | 33h | 18.6 V |
| 04h | 13.9 V | 14h | 15.5 V | 24h | 17.1 V | 34h | 18.7 V |
| 05h | 14.0 V | 15h | 15.6 V | 25h | 17.2 V | 35h | 18.8 V |
| 06h | 14.1 V | 16h | 15.7 V | 26h | 17.3 V | 36h | 18.9 V |
| 07h | 14.2 V | 17h | 15.8 V | 27h | 17.4 V | 37h | 19.0 V |
| 08h | 14.3 V | 18h | 15.9 V | 28h | 17.5 V | 38h | 19.1 V |
| 09h | 14.4 V | 19h | 16.0 V | 29h | 17.6 V | 39h | 19.2 V |
| 0Ah | 14.5 V | 1Ah | 16.1 V | 2Ah | 17.7 V | 3Ah | 19.3 V |
| 0Bh | 14.6 V | 1Bh | 16.2 V | 2Bh | 17.8 V | 3Bh | 19.4 V |
| 0Ch | 14.7 V | 1Ch | 16.3 V | 2Ch | 17.9 V | 3Ch | 19.5 V |
| 0Dh | 14.8 V | 1Dh | 16.4 V | 2Dh | 18.0 V | 3Dh | 19.6 V |
| 0Eh | 14.9 V | 1Eh | 16.5 V | 2Eh | 18.1 V | 3Eh | 19.7 V |
| 0Fh | 15.0 V | 1Fh | 16.6 V | 2Fh | 18.2 V | 3Fh | 19.8 V |
7.7.1.3 Boost HVS Offset Voltage Register (with factory value) – 02h (05h)
| MSB | Address 01h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | Reserved | 0 | 1 | 0 | 1 |
| DAC Value | V(OFFSET) | DAC Value | V(OFFSET) | DAC Value | V(OFFSET) | DAC Value | V(OFFSET) |
|---|---|---|---|---|---|---|---|
| 00h | 0.0 V | 04h | 0.8 V | 08h | 1.6 V | 0Ch | 2.4 V |
| 01h | 0.2 V | 05h | 1.0 V | 09h | 1.8 V | 0Dh | 2.6 V |
| 02h | 0.4 V | 06h | 1.2 V | 0Ah | 2.0 V | 0Eh | 2.8 V |
| 03h | 0.6 V | 07h | 1.4 V | 0Bh | 2.2 V | 0Fh | 3.0 V |
7.7.1.4 Boost Current Limit Negative Offset Current Register (with factory value) – 03h (00h)
| MSB | Address 03h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | Reserved | Reserved | 0 | 0 | 0 |
| DAC Value | I(OFFSET) | DAC Value | I(OFFSET) | DAC Value | I(OFFSET) | DAC Value | I(OFFSET) |
|---|---|---|---|---|---|---|---|
| 00h | 0.0 A | 02h | 0.8 A | 04h | 1.6 A | 06h | 2.4 A |
| 01h | 0.4 A | 03h | 1.2 A | 05h | 2.0 A | 07h | 2.8 A |
7.7.1.5 Boost Soft-start Time Register (with factory value) – 04h (00h)
| MSB | Address 04h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | 0 |
| DAC Value | Time |
|---|---|
| 00h | 10 ms |
| 01h | 20 ms |
7.7.1.6 Buck 1 Output Voltage V(IO) Register (with factory value) – 05h (03h):
| MSB | Address 05h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | Reserved | 0 | 0 | 1 | 1 |
| DAC Value | V(IO) | DAC Value | V(IO) | DAC Value | V(IO) | DAC Value | V(IO) |
|---|---|---|---|---|---|---|---|
| 00h | 2.2 V | 04h | 2.6 V | 08h | 3.0 V | 0Ch | 3.4 V |
| 01h | 2.3 V | 05h | 2.7 V | 09h | 3.1 V | 0Dh | 3.5 V |
| 02h | 2.4 V | 06h | 2.8 V | 0Ah | 3.2 V | 0Eh | 3.6 V |
| 03h | 2.5 V | 07h | 2.9 V | 0Bh | 3.3 V | 0Fh | 3.7 V |
7.7.1.7 Buck 2 Output Voltage V(CORE) Register (with factory value) – 06h (02h)
| MSB | Address 06h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | 0 | 0 | 0 | 1 | 0 |
| DAC Value | V(CORE) | DAC Value | V(CORE) | DAC Value | V(CORE) | DAC Value | V(CORE) |
|---|---|---|---|---|---|---|---|
| 00h | 0.8 V | 07h | 1.5 V | 0Eh | 2.2 V | 15h | 2.9 V |
| 01h | 0.9 V | 08h | 1.6 V | 0Fh | 2.3 V | 16h | 3.0 V |
| 02h | 1.0 V | 09h | 1.7 V | 10h | 2.4 V | 17h | 3.1 V |
| 03h | 1.1 V | 0Ah | 1.8 V | 11h | 2.5 V | 18h | 3.2 V |
| 04h | 1.2 V | 0Bh | 1.9 V | 12h | 2.6 V | 19h | 3.3 V |
| 05h | 1.3 V | 0Ch | 2.0 V | 13h | 2.7 V | ||
| 06h | 1.4 V | 0Dh | 2.1 V | 14h | 2.8 V |
7.7.1.8 Buck 3 Output Voltage V(HAVDD) Register (with factory value) – 07h (1Bh)
| MSB | Address 07h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | 0 | 1 | 1 | 0 | 1 | 1 |
| DAC Value | V(HAVDD) | DAC Value | V(HAVDD) | DAC Value | V(HAVDD) | DAC Value | V(HAVDD) |
|---|---|---|---|---|---|---|---|
| 00h | 4.8 V | 10h | 6.4 V | 20h | 8.0 V | 30h | 9.6 V |
| 01h | 4.9 V | 11h | 6.5 V | 21h | 8.1 V | 31h | 9.7 V |
| 02h | 5.0 V | 12h | 6.6 V | 22h | 8.2 V | 32h | 9.8 V |
| 03h | 5.1 V | 13h | 6.7 V | 23h | 8.3 V | 33h | 9.9 V |
| 04h | 5.2 V | 14h | 6.8 V | 24h | 8.4 V | 34h | 10.0 V |
| 05h | 5.3 V | 15h | 6.9 V | 25h | 8.5 V | 35h | 10.1 V |
| 06h | 5.4 V | 16h | 7.0 V | 26h | 8.6 V | 36h | 10.2 V |
| 07h | 5.5 V | 17h | 7.1 V | 27h | 8.7 V | 37h | 10.3 V |
| 08h | 5.6 V | 18h | 7.2 V | 28h | 8.8 V | 38h | 10.4 V |
| 09h | 5.7 V | 19h | 7.3 V | 29h | 8.9 V | 39h | 10.5 V |
| 0Ah | 5.8 V | 1Ah | 7.4 V | 2Ah | 9.0 V | 3Ah | 10.6 V |
| 0Bh | 5.9 V | 1Bh | 7.5 V | 2Bh | 9.1 V | 3Bh | 10.7 V |
| 0Ch | 6.0 V | 1Ch | 7.6 V | 2Ch | 9.2 V | 3Ch | 10.8 V |
| 0Dh | 6.1 V | 1Dh | 7.7 V | 2Dh | 9.3 V | 3Dh | 10.9 V |
| 0Eh | 6.2 V | 1Eh | 7.8 V | 2Eh | 9.4 V | 3Eh | 11.0 V |
| 0Fh | 6.3 V | 1Fh | 7.9 V | 2Fh | 9.5 V | 3Fh | 11.1 V |
7.7.1.9 Pos. Charge Pump Low Output Voltage V(GH_L) Register (with factory value) – 08h (08h):
| MSB | Address 08h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | Reserved | 1 | 0 | 0 | 0 |
| DAC Value | V(GH_L) | DAC Value | V(GH_L) | DAC Value | V(GH_L) | DAC Value | V(GH_L) |
|---|---|---|---|---|---|---|---|
| 00h | 20 V | 04h | 24 V | 08h | 28 V | 0Ch | 32 V |
| 01h | 21 V | 05h | 25 V | 09h | 29 V | 0Dh | 33 V |
| 02h | 22 V | 06h | 26 V | 0Ah | 30 V | 0Eh | 34 V |
| 03h | 23 V | 07h | 27 V | 0Bh | 31 V | 0Fh | 35 V |
7.7.1.10 Positive Charge Pump Low Output Voltage V(GH_L) to V(GH_H) Positive Offset Voltage V(GH_OFS) Register (with factory value) – 09h (04h):
| MSB | Address 09h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | Reserved | 0 | 1 | 0 | 0 |
| DAC Value | V(GH_L) | DAC Value | V(GH_L) | DAC Value | V(GH_L) | DAC Value | V(GH_L) |
|---|---|---|---|---|---|---|---|
| 00h | 0 V | 04h | 4 V | 08h | 8 V | 0Ch | 12 V |
| 01h | 1 V | 05h | 5 V | 09h | 9 V | 0Dh | 13 V |
| 02h | 2 V | 06h | 6 V | 0Ah | 10 V | 0Eh | 14 V |
| 03h | 3 V | 07h | 7 V | 0Bh | 11 V | 0Fh | 15 V |
7.7.1.11 Gate Pulse Modulation Limit Voltage Register (with factory value) – 0Ah (00h)
| MSB | Address 0Ah | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | 0 | 0 |
| DAC Value | Limit | DAC Value | Limit |
|---|---|---|---|
| 00h | 0 V | 02h | 10 V |
| 01h | 5 V | 03h | 15 V |
7.7.1.12 Negative Charge Pump Output Voltage V(GL) Register (with factory value) – 0Bh (04h)
| MSB | Address 05h | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | Reserved | 0 | 1 | 0 | 0 |
| DAC Value | V(GL) | DAC Value | V(GL) | DAC Value | V(GL) | DAC Value | V(GL) |
|---|---|---|---|---|---|---|---|
| 00h | –5.5 V | 04h | –7.9 V | 08h | –10.3 V | 0Ch | –12.7 V |
| 01h | –6.1 V | 05h | –8.5 V | 09h | –10.9 V | 0Dh | –13.3 V |
| 02h | –6.7 V | 06h | –9.1 V | 0Ah | –11.5 V | 0Eh | –13.9 V |
| 03h | –7.3 V | 07h | –9.7 V | 0Bh | –12.1 V | 0Fh | –14.5 V |
7.7.1.13 Buck 3 HVS Offset Voltage Register (with factory value) – 0Ch (00h):
| MSB | Address 0Ch | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | Reserved | 0 | 0 | 0 | 0 |
| DAC Value | V(OFFSET) | DAC Value | V(OFFSET) | DAC Value | V(OFFSET) | DAC Value | V(OFFSET) |
|---|---|---|---|---|---|---|---|
| 00h | 0.0 V | 04h | 0.4 V | 08h | 0.8 V | 0Ch | 1.2 V |
| 01h | 0.1 V | 05h | 0.5 V | 09h | 0.9 V | 0Dh | 1.3 V |
| 02h | 0.2 V | 06h | 0.6 V | 0Ah | 1.0 V | 0Eh | 1.4 V |
| 03h | 0.3 V | 07h | 0.7 V | 0Bh | 1.1 V | 0Fh | 1.5 V |
7.7.1.14 Memory Write Remain Time Register (with factory value) – FEh (0Fh):
| MSB | Address FEh | LSB | |||||
|---|---|---|---|---|---|---|---|
| Reserved | Reserved | Reserved | Reserved | 1 | 1 | 1 | 1 |
| DAC Value | Remaining Writes | DAC Value | Remaining Writes | DAC Value | Remaining Writes | DAC Value | Remaining Writes |
|---|---|---|---|---|---|---|---|
| 00h | 0 | 04h | 4 | 08h | 8 | 0Ch | 12 |
| 01h | 1 | 05h | 5 | 09h | 9 | 0Dh | 13 |
| 02h | 2 | 06h | 6 | 0Ah | 10 | 0Eh | 14 |
| 03h | 3 | 07h | 7 | 0Bh | 11 | 0Fh | EEPROM |