7.3.1.1.1 AC- and DC-Coupled Modes

The analog inputs may be AC- or DC-coupled. See AC-DC-Coupled Mode Pin (VCMO) for information on how to select the desired mode; see DC-Coupled Input Signals and AC-Coupled Input Signals for applications information.

7.3.1.1.2 Input Full-Scale Range Adjust

The input full-scale range for the ADC10D1000 may be adjusted via non-ECM or ECM. In non-ECM, a control pin selects a higher or lower value; see Full-Scale Input Range Pin (FSR). In ECM, the input full-scale range may be selected with 15 bits of precision; see V_{IN_FSR} in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics, for details. Note that the higher and lower full-scale input range settings in non-ECM do not correspond to the maximum and minimum full-scale input range settings in ECM. It is necessary to execute a manual calibration following any change of the input full-scale range. See Register Maps for information about the registers.

7.3.1.1.3 Input Offset Adjust

The input offset adjust for the ADC10D1000 may be adjusted with 12 bits of precision plus sign via ECM. See Register Maps for information about the registers.

7.3.1.1.4 DES/Non-DES Mode

The ADC10D1000 is available in dual-edge sampling (DES) or non-DES mode. The DES mode allows for the device Q-channel input to be sampled by the ADCs of both channels. One ADC samples the input on the rising edge of the input clock and the other ADC samples the same input on the falling edge of the input clock. A single input is thus sampled twice per input clock cycle, resulting in an overall sample rate of twice the input clock frequency, for example, 2 GSPS with a 1-GHz input clock. See for information on how to select the desired mode.

For the DES mode, only the Q channel may be used for the input. This may be selected in ECM by using the DES bit (Addr: 0h, Bit 7) to select the DES mode and the DESQ bit (Addr: 0h, Bit: 6) to select the Q channel as input.

In this mode, the outputs must be carefully interleaved in order to reconstruct the sampled signal. If the device is programmed into the 1:4 Demux DES mode, the data is effectively demultiplexed by 1:4. If the input clock is 1 GHz, the effective sampling rate is doubled to 2 GSPS, and each of the 4 output buses has an output rate of 500 MHz. All data is available in parallel. To properly reconstruct the sampled waveform, the four words of parallel data that are output with each DCLK must be correctly interleaved. The sampling order is as follows, from the earliest to the latest: DQd, DId, DQ, DI. See Figure 1. If the device is programmed into the non-demux DES mode, two bytes of parallel data are output with each edge of the DCLK in the following sampling order, from the earliest to the latest: DQ, DI. See Figure 4.

The performance of the ADC10D1000 in DES mode depends on how well the two channels are interleaved; that is, that the clock samples each channel with precisely a 50% duty cycle, each channel has the same offset (nominally code 511/512), and each channel has the same full-scale range. The ADC10D1000 also includes an automatic clock phase background adjustment in DES mode to automatically and continuously adjust the clock phase of the I and Q channels. This feature removes the need to adjust the clock phase setting manually and provides optimal performance in the DES mode. A difference exists in the typical offset between the I and Q channels, which can be removed via the offset adjust feature in ECM to optimize DES mode performance. To adjust the I- and Q-channel offset, measure a histogram of the digital data and adjust the offset via the control register until the histogram is centered at code 511/512. Similarly, the full-scale range of each channel may be adjusted for optimal performance.

7.3.1.1.5 Sampling Clock Phase Adjust

The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature is intended to help the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs are used, or simplify complex system functions such as beam steering for phase array antennas. A clock-jitter cleaner is available only when the CLK phase adjust feature is used. This adjustment delays all clocks, including the DCLKs and output data, and the user is strongly advised to use the minimal amount of adjustment and verify the net benefit of this feature in the system before relying on it.

7.3.1.1.6 LC Filter-On Input Clock

An LC bandpass filter is available on the ADC10D1000 sampling clock to clean jitter on the incoming clock. This feature is available when the CLK phase adjust is also used. This feature was designed to minimize the dynamic performance degradation resulting from additional clock jitter as much as possible. This feature is available in ECM via the LC filter (LCF) bits in the Control Register (Addr: Dh, Bits 7:0).

If the clock phase adjust feature is enabled, the sampling clock passes through additional gate delay, which adds jitter to the clock signal; the LCF helps to remove this additional jitter, so it is only available when the clock phase adjust feature is also enabled. To enable both features, use SA (Addr: Dh, Bit 8). The LCF bits are thermometer encoded and may be used to set a filter center frequency ranging from 0.8 GHz to 1.5 GHz; see Table 2.

The LC filter is a second-order bandpass filter, which has the following simulated bandwidth for a center frequency, f_c at 1 GHz (see Table 3).

7.3.1.1.7 V_CMO Adjust

The V_CMO of the ADC10D1000QML is generated as a buffered version of the internal bandgap reference; see AC-DC-Coupled Mode Pin (VCMO). This pin provides an output voltage, which is the optimal common-mode voltage for the input signal and should be used to set the common-mode voltage of the driving buffer. However, in order to accommodate larger signals at the analog inputs, the V_CMO may be adjusted to a lower value. From its typical default value, the V_CMO may be lowered by approximately 200 mV via the VCA(2:0) bits of the Control Register (Addr: 1h; Bits: 7:5) in ECM. See Register Definitions for more information. Adjusting the V_CMO away from its optimal value also degrades the dynamic performance; see V_CMO in Recommended Operating Conditions.

7.3.1.2.1 DDR Clock Phase

The ADC10D1000 output data is always delivered in double data rate (DDR). With DDR, the DCLK frequency is half the data rate and data is sent to the outputs on both edges of DCLK; see Figure 39. The DCLK-to-data phase relationship may be either 0° or 90°. For 0° mode, the data transitions on each edge of the DCLK. Any offset from this timing is t_OSK; see Converter Electrical Characteristics: AC Electrical Characteristics for details. For 90° mode, the DCLK transitions in the middle of each data cell. Setup and hold times for this transition, t_SU and t_H, may also be found in Converter Electrical Characteristics: AC Electrical Characteristics. The DCLK-to-data phase relationship may be selected via the DDRPh Pin in Non-ECM (see Dual Data-Rate Phase Pin (DDRPh)) or the DPS bit in the Configuration Register (Addr: 0h; Bit: 14) in ECM.

Figure 39. DDR DCLK-to-Data Phase Relationship

7.3.1.2.2 LVDS Output Differential Voltage

The ADC10D1000 is available with a selectable higher or lower LVDS output differential voltage. This parameter is V_OD and may be found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. The desired voltage may be selected via OVS Bit (Addr: 0h, Bit 13); see Register Maps for more information. In non-extended control mode only higher V_OD is available.

7.3.1.2.3 LVDS Output Common-Mode Voltage

The ADC10D1000 is available with a selectable higher or lower LVDS output common-mode voltage. This parameter is V_OS and may be found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. See LVDS Output Common-Mode Pin (VBG) for information on how to select the desired voltage.

7.3.1.2.4 Output Formatting

The formatting at the digital data outputs may be either offset binary or two's complement. The desired formatting is set via the 2SC bit of the Control Register (Addr: 0h; Bit: 4) in ECM; see Register Maps for more information.

7.3.1.2.5 Demux/Non-Demux Mode

The ADC10D1000 may be in one of two demultiplex modes: demux mode or non-demux mode (also sometimes referred to as 1:1 demux mode). In non-demux mode, the data from the input is simply output at the sampling rate at which it was sampled on one 10-bit bus. In demux mode, the data from the input is output at half the sampling rate, on twice the number of buses (see Functional Block Diagram). Demux or non-demux mode may only be selected by the NDM pin; see Non-Demultiplexed Mode Pin (NDM). In non-DES mode, the output data from each channel may be demultiplexed by a factor of 1:2 (1:2 demux non-DES mode). In DES mode, the output data from both channels interleaved may be demultiplexed (1:4 demux DES mode) or not demultiplexed (non-demux DES mode).

7.3.1.2.6 Test Pattern Mode

The ADC10D1000 can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In test-pattern mode, the ADC is disengaged, and a test pattern generator is connected to the outputs, including ORI and ORQ. The test pattern output is the same in DES mode or non-DES mode. Each port is given a unique 10-bit word, alternating between 1's and 0's. When the device is programmed into the demux mode, the order of the test pattern is as described in Table 4.

When the device is programmed into the non-demux mode, the order of the test pattern is as described in Table 5.

7.3.1.3.1 Calibration Pins

Table 6 is a summary of the pins used for calibration. See Pin Configuration and Functions for complete pin information and Figure 6 for the timing diagram.

7.3.1.3.2 How to Initiate a Calibration Event

The calibration event must be initiated by holding the CAL pin low for at least t_{CAL_L} clock cycles, and then holding it high for at least another t_{CAL_H} clock cycles, as defined in Timing Requirements: Calibration. The minimum t_{CAL_L} and t_{CAL_H} input clock cycle sequences are required to ensure that random noise does not cause a calibration to begin when it is not desired. The time taken by the calibration procedure is specified as t_CAL. In ECM, either the CAL bit (Addr: 0h; Bit: 15) or the CAL pin may be used to initiate a calibration event.

7.3.1.3.3 On-Command Calibration

An on-command calibration must be run after power up and whenever the FSR is changed. TI recommends execution of an on-command calibration whenever the settings or conditions to the device are altered significantly, in order to obtain optimal parametric performance. Some examples include: changing the FSR via either ECM or non-ECM, power-cycling either channel, and switching into or out of DES mode. For best performance, it is also recommended that an on-command calibration be run 20 seconds or more after application of power and whenever the operating temperature changes significantly, relative to the specific system performance requirements.

Due to the nature of the calibration feature, TI recommends avoiding unnecessary activities on the device while the calibration is taking place. For example, do not read or write to the serial interface or use the DCLK reset feature while calibrating the ADC. Doing so impairs the performance of the device until it is re-calibrated correctly. Also, it is recommended to not apply a strong narrow-band signal to the analog inputs during calibration because this may impair the accuracy of the calibration; broad spectrum noise is acceptable.

7.3.1.3.4 Calibration Adjust

The calibration event itself may be adjusted, for sequence and mode. This feature can be used if a shorter calibration time than the default is required; see t_CAL in Timing Requirements: Calibration. However, the performance of the device, when using a shorter calibration time than the default setting, is not ensured.

The calibration sequence may be adjusted via CSS (Addr: 4h, bit 14). The default setting of CSS = 1b executes both R_IN and R_IN_CLK calibration (using Rtrim) and internal linearity calibration (using Rext). Executing a calibration with CSS = 0b executes only the internal linearity calibration. The first time that calibration is executed, it must be with CSS = 1b to trim R_IN and R_IN_CLK. However, once the device is at its operating temperature, and R_IN has been trimmed at least one time, it does not drift significantly. To save time in subsequent calibrations, trimming R_IN and R_IN_CLK may be skipped — that is, by setting CSS = 0b.

The mode may be changed, to save calibration execution time for the internal linearity calibration. See t_CAL in Converter Electrical Characteristics: AC Electrical Characteristics. Adjusting the CMS(1:0) bits of the Calibration Adjust Register (Addr: 4h; Bits: 9:8) selects three different pre-defined calibration times. A longer of time calibrates each channel more closely to the ideal values, but choosing shorter times does not significantly impact the performance. The fourth setting, CMS(1:0) = 11b, is not available.

7.3.1.3.5 Calibration and Power Down

If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC10D1000 immediately powers down. The calibration cycle continues when either or both channels are powered back up, but the calibration is compromised due to the incomplete settling of bias currents directly after power up. Therefore, a new calibration must be executed upon powering the ADC10D1000 back up. In general, the ADC10D1000 must be re-calibrated when either or both channels are powered back up, or after one channel is powered down. For best results, power back up after the device has stabilized to its operating temperature.

7.3.1.3.6 Read/Write Calibration Settings

When the ADC performs a calibration, the calibration constants are stored in an array which is accessible via the Calibration Values Register (Addr: 5h). To save the time that it takes to execute a calibration, t_CAL, or if re-using a previous calibration result, these values can be read from and written to the register at a later time. For example, if an application requires the same input impedance, R_IN, this feature can be used to load a previously determined set of values. For the calibration values to be valid, the ADC must be operating under the same conditions, including temperature, at which the calibration values were originally read from the ADC.

To read calibration values from the SPI, do the following:

1. Set ADC to desired operating conditions.
2. Set SSC (Addr: 4h, Bit 7) to 1
3. Read exactly 184 times the Calibration Values Register (Addr: 5h). The register values are R0, R1, R2... R183 where R0 is a dummy value. The contents of R <183:1> must be stored.
4. Set SSC (Addr: 4h, Bit 7) to 0.
5. Continue with normal operation.

To write calibration values to the SPI, do the following:

1. Set ADC to operating conditions at which calibration values were previously read.
2. Set SSC (Addr: 4h, Bit 7) to 1.
3. Write exactly 183 times the Calibration Values Register (Addr: 5h). The registers should be written with stored register values R1, R2... R183.
4. Make two additional dummy writes of 0000h.
5. Set SSC (Addr: 4h, Bit 7) to 0.
6. Continue with normal operation.

Table 7. Non-ECM Pin Summary

7.4.1.1.1 Non-Demultiplexed Mode Pin (NDM)

The non-demultiplexed mode (NDM) pin selects whether the ADC10D1000 is in demux mode (logic-low) or non-demux mode (logic-high). In Non-demux mode, the data from the input is produced at the data-rate at a single 10-bit output bus. In demux mode, the data from the input is produced at half the data-rate at twice the number of output buses. For non-des mode, each I or Q channel produces its data on one or two buses for non-demux mode or demux mode, respectively. For DES mode, the Q channel produces its data on two or four buses for non-demux mode or demux mode, respectively.

This feature is pin-controlled only and remains active during both non-ECM and ECM. See Table 7 for more information.

7.4.1.1.2 Dual Data-Rate Phase Pin (DDRPh)

The dual data-rate-phase (DDRPh) pin selects whether the ADC10D1000 is in 0° mode (logic-low) or 90° mode (logic-high). In dual data rate (DDR) mode, the data may transition either with the DCLK transition (0° mode) or halfway between DCLK transitions (90° mode). The data is always in DDR mode on the ADC10D1000. The DDRPh pin selects 0° mode or 90° mode for both the I-channel DI- and DId-to-DCLKI phase relationship and for the Q-channel DQ- and DQd-to-DCLKQ phase relationship.

To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See Table 11 for more information.

7.4.1.1.3 Calibration Pin (CAL)

The calibration pin (CAL) must be used to initiate an on-command calibration event. The effect of calibration is to maximize the dynamic performance. To initiate an on-command calibration via the CAL pin, bring the CAL pin high for a minimum of t_{CAL_H} input clock cycles after it has been low for a minimum of t_{CAL_L} input clock cycles. Hold the CAL pin high when not in use to ensure no undesired calibrating in space environment. In ECM mode this pin remains active and is logically OR'd with the CAL bit.

To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See Calibration Feature for more information.

7.4.1.1.4 Power-Down I-Channel Pin (PDI)

The power-down I-channel (PDI) pin selects whether the I channel is powered down (logic-high) or active (logic-low). The digital data output pins (both positive and negative) are put into a high impedance state when the I channel is powered down. Upon return to the active state, the pipeline contains meaningless information and must be flushed. The supply currents (typicals and limits) are available for the I channel powered down or active and may be found in Converter Electrical Characteristics: Power Supply Characteristics (1:2 Demux Mode). It is recommended that the user thoroughly understand how the PDI feature functions in relationship with the Calibration feature and control them appropriately for their application.

This pin remains active in ECM. In ECM, either this pin or the PDI bit (Addr: 0h; Bit: 11) in the Control Register may be used to power down the I channel. See Power Down for more information.

7.4.1.1.5 Power-Down Q-Channel Pin (PDQ)

The power-down Q-channel (PDQ) pin selects whether the Q- channel is powered down (logic-high) or active (logic-low). This pin functions similarly to the PDI pin, except that it applies to the Q channel. The PDI and PDQ pins function independently of each other to control whether each I channel or Q channel is powered down or active.

This pin remains active in ECM. In ECM, either this pin or the PDQ bit (Addr: 0h; Bit: 10) in the Control Register may be used to power-down the I channel. See Power Down for more information.

7.4.1.1.6 Test Pattern Mode Pin (TPM)

The test-pattern mode (TPM) pin selects whether the output of the ADC10D1000 is a test pattern (logic-high) or the converted input (logic-low). The ADC10D1000 can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In TPM, the ADC is disengaged, and a test pattern generator is connected to the outputs, including ORI and ORQ. See Test Pattern Mode for more information.

7.4.1.1.7 Full-Scale Input Range Pin (FSR)

The full-scale input range (FSR) pin selects whether the full-scale input range for both the I channel and Q channel is higher (logic-high) or lower (logic-low). The input full-scale range is specified as V_{IN_FSR} in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics. In non-ECM, the full-scale input range for each I channel and Q channel may not be set independently, but it is possible to do so in ECM. The device must be calibrated following a change in FSR to obtain optimal performance.

To use this feature in ECM, use the Configuration Register (Addr: 3h and Bh). See Input Control and Adjust for more information.

7.4.1.1.8 AC-DC-Coupled Mode Pin (V_CMO)

The V_CMO pin serves a dual purpose. When functioning as an output, it provides the optimal common-mode voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the device is AC-coupled (logic-low) or DC-coupled (floating). This pin is always active, in both ECM and non-ECM.

7.4.1.1.9 LVDS Output Common-Mode Pin (V_BG)

The V_BG pin serves a dual purpose and may either provide the bandgap output voltage or select whether the LVDS output common-mode voltage is higher (logic-high) or lower (floating). The LVDS output common-mode voltage is specified as V_OS and may be found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. This pin is always active, in both ECM and Non-ECM. See Output Control and Adjust for more information.