5.3.1.1 AC/DC-coupled Mode

The analog inputs may be AC or DC-coupled. See Section 5.5.1.1.10 for information on how to select the desired mode and Section 6.1.1.7 and Section 6.1.1.6 for applications information.

5.3.1.2 Input Full-Scale Range Adjust

The input full-scale range for the ADC12D1800RF may be adjusted in ECM. In Non-ECM, the control pin must be set to logic-high; see Section 5.5.1.1.9. In ECM, the input full-scale range may be adjusted with 15-bits of precision. See V_{IN_FSR} in Section 4.7 for electrical specification details. Note that the full-scale input range setting in Non-ECM (logic-high only) corresponds to the lowest full-scale input range settings in ECM. It is necessary to execute an on-command calibration following a change of the input full-scale range. See Section 5.6.1 for information about the registers.

5.3.1.3 Input Offset Adjust

The input offset adjust for the ADC12D1800RF may be adjusted with 12-bits of precision plus sign via ECM. See Section 5.6.1 for information about the registers.

5.3.1.4 DES Timing Adjust

The performance of the ADC12D1800RF in DES Mode depends on how well the two channels are interleaved, i.e. that the clock samples either channel with precisely a 50% duty-cycle, each channel has the same offset (nominally code 2047/2048), and each channel has the same full-scale range. The ADC12D1800RF includes an automatic clock phase background adjustment in DES Mode to automatically and continuously adjust the clock phase of the I- and Q-channels. In addition to this, the residual fixed timing skew offset may be further manually adjusted, and further reduce timing spurs for specific applications. See the Table 5-17 (Addr: 7h). As the DES Timing Adjust is programmed from 0d to 127d, the magnitude of the Fs/2-Fin timing interleaving spur will decrease to a local minimum and then increase again. The default, nominal setting of 64d may or may not coincide with this local minimum. The user may manually skew the global timing to achieve the lowest possible timing interleaving spur.

5.3.1.5 Sampling Clock Phase (Aperture) Delay Adjust

The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature is intended to help the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs are used, or to simplify complex system functions such as beam steering for phase array antennas.

Additional delay in the clock path also creates additional jitter when using the sampling clock phase adjust. Because the sampling clock phase adjust delays all clocks, including the DCLKs and output data, the user is strongly advised to use the minimal amount of adjustment and verify the net benefit of this feature in his system before relying on it.

Using this feature at its maximum setting, for the maximum sampling clock rate, may affect the integrity of the sampling clock on chip. Therefore, it is not recommended to do so. The maximum setting for the coarse adjust is 825ps. The period for the maximum sampling clock rate of is 555ps, so it should not be necessary to exceed this value in any case.

5.3.2.1 SDR / DDR Clock

The ADC12D1800RF output data can be delivered in Double Data Rate (DDR) or Single Data Rate (SDR). For DDR, the DCLK frequency is half the data rate and data is sent to the outputs on both edges of DCLK; see Figure 5-3. The DCLK-to-Data phase relationship may be either 0° or 90°. For 0° Mode, the Data transitions on each edge of the DCLK. Any offset from this timing is t_OSK; see Section 4.13 for details. For 90° Mode, the DCLK transitions in the middle of each Data cell. Setup and hold times for this transition, t_SU and t_H, may also be found in Section 4.13. The DCLK-to-Data phase relationship may be selected via the DDRPh Pin in Non-ECM (see Section 5.5.1.1.3) or the DPS bit in the Configuration Register (Addr: 0h; Bit: 14) in ECM. Note that for Non-Demux Mode, 90° DDR Mode is not available.

Figure 5-3 DDR DCLK-to-Data Phase Relationship

For SDR, the DCLK frequency is the same as the data rate and data is sent to the outputs on a single edge of DCLK; see Figure 5-4. The Data may transition on either rising or falling edge of DCLK. Any offset from this timing is t_OSK; see Section 4.13 for details. The DCLK rising / falling edge may be selected via the SDR bit in the Configuration Register (Addr: 0h; Bit: 2) in ECM only. Note that SDR is available in Demux Mode, but not in Non-Demux Mode.

Figure 5-4 SDR DCLK-to-Data Phase Relationship

5.3.2.2 LVDS Output Differential Voltage

The ADC12D1800RF is available with a selectable higher or lower LVDS output differential voltage. This parameter is V_OD and may be found in Section 4.11. The desired voltage may be selected via the OVS Bit (Addr: 0h, Bit 13). For many applications, in which the LVDS outputs are very close to an FPGA on the same board, for example, the lower setting is sufficient for good performance; this will also reduce the possibility for EMI from the LVDS outputs to other signals on the board. See Section 5.6.1 for more information.

5.3.2.3 LVDS Output Common-Mode Voltage

The ADC12D1800RF is available with a selectable higher or lower LVDS output common-mode voltage. This parameter is V_OS and may be found in Section 4.11. See Section 5.5.1.1.11 for information on how to select the desired voltage.

5.3.2.4 Output Formatting

The formatting at the digital data outputs may be either offset binary or two's complement. The default formatting is offset binary, but two's complement may be selected via the 2SC Bit (Addr: 0h, Bit 4); see Section 5.6.1 for more information.

5.3.2.5 Test Pattern Mode

The ADC12D1800RF can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In Test Pattern Mode, the ADC is disengaged and a test pattern generator is connected to the outputs, including ORI and ORQ. The test pattern output is the same in DES Mode or Non-DES Mode. Each port is given a unique 12-bit word, alternating between 1's and 0's. When the part is programmed into the Demux Mode, the test pattern’s order is described in Table 5-2. If the I- or Q-channel is powered down, the test pattern will not be output for that channel.

5.3.2.6 Time Stamp

The Time Stamp feature enables the user to capture the timing of an external trigger event, relative to the sampled signal. When enabled via the TSE Bit (Addr: 0h; Bit: 3), the LSB of the digital outputs (DQd, DQ, DId, DI) captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. The trigger should be applied to the DCLK_RST input. It may be asynchronous to the ADC sampling clock.

5.3.3.1 Calibration Control Pins and Bits

Table 5-4 is a summary of the pins and bits used for calibration. See Section 3.1.1 for complete pin information and Figure 4-7 for the timing diagram.

5.3.3.2 How to Execute a Calibration

Calibration may be initiated by holding the CAL pin low for at least t_{CAL_L} clock cycles, and then holding it high for at least another t_{CAL_H} clock cycles, as defined in Section 4.15. The minimum t_{CAL_L} and t_{CAL_H} input clock cycle sequences are required to ensure that random noise does not cause a calibration to begin when it is not desired. The time taken by the calibration procedure is specified as t_CAL. The CAL Pin is active in both ECM and Non-ECM. However, in ECM, the CAL Pin is logically OR'd with the CAL Bit, so both the pin and bit are required to be set low before executing another calibration via either pin or bit.

5.3.3.3 Power-on Calibration

For standard operation, power-on calibration begins after a time delay following the application of power, as determined by the setting of the CalDly Pin and measured by t_CalDly (see Section 4.15). This delay allows the power supply to come up and stabilize before the power-on calibration takes place. The best setting (short or long) of the CalDly Pin depends upon the settling time of the power supply.

It is strongly recommended to set CalDly Pin (to either logic-high or logic-low) before powering the device on since this pin affects the power-on calibration timing. This may be accomplished by setting CalDly via an external 1kΩ resistor connected to GND or V_A. If the CalDly Pin is toggled while the device is powered-on, it can execute a calibration even though the CAL Pin / Bit remains logic-low.

The power-on calibration will be not be performed if the CAL pin is logic-high at power-on. In this case, the calibration cycle will not begin until the on-command calibration conditions are met. The ADC12D1800RF will function with the CAL pin held high at power up, but no calibration will be done and performance will be impaired.

If it is necessary to toggle the CalDly Pin during the system power up sequence, then the CAL Pin / Bit must be set to logic-high before the toggling and afterwards for 10⁹ Sampling Clock cycles. This will prevent the power-on calibration, so an on-command calibration must be executed or the performance will be impaired.

5.3.3.4 On-command Calibration

In addition to the power-on calibration, it is recommended to execute an on-command calibration whenever the settings or conditions to the device are altered significantly, in order to obtain optimal parametric performance. Some examples include: changing the FSR via ECM, power-cycling either channel, and switching into or out of DES Mode. For best performance, it is also recommended that an on-command calibration be run 20 seconds or more after application of power and whenever the operating temperature changes significantly, relative to the specific system performance requirements.

Due to the nature of the calibration feature, it is recommended to avoid unnecessary activities on the device while the calibration is taking place. For example, do not read or write to the Serial Interface or use the DCLK Reset feature while calibrating the ADC. Doing so will impair the performance of the device until it is re-calibrated correctly. Also, it is recommended to not apply a strong narrow-band signal to the analog inputs during calibration because this may impair the accuracy of the calibration; broad spectrum noise is acceptable.

5.3.3.5 Calibration Adjust

The sequence of the calibration event itself may be adjusted. This feature can be used if a shorter calibration time than the default is required; see t_CAL in Section 4.15. However, the performance of the device, when using this feature is not ensured.

The calibration sequence may be adjusted via CSS (Addr: 4h, Bit 14). The default setting of CSS = 1b executes both R_IN and R_{IN_CLK} Calibration (using Rtrim) and internal linearity Calibration (using Rext). Executing a calibration with CSS = 0b executes only the internal linearity Calibration. The first time that Calibration is executed, it must be with CSS = 1b to trim R_IN and R_{IN_CLK}. However, once the device is at its operating temperature and R_IN has been trimmed at least one time, it will not drift significantly. To save time in subsequent calibrations, trimming R_IN and R_{IN_CLK} may be skipped, i.e. by setting CSS = 0b.

5.3.3.6 Read / Write Calibration Settings

When the ADC performs a calibration, the calibration constants are stored in an array which is accessible via the Calibration Values register (Addr: 5h). To save the time which it takes to execute a calibration, t_CAL, or to allow for re-use of a previous calibration result, these values can be read from and written to the register at a later time. For example, if an application requires the same input impedance, R_IN, this feature can be used to load a previously determined set of values. For the calibration values to be valid, the ADC must be operating under the same conditions, including temperature, at which the calibration values were originally determined by the ADC.

To read calibration values from the SPI, do the following:

1. Set ADC to desired operating conditions.

2. Set SSC (Addr: 4h, Bit 7) to 1.

3. Read exactly 240 times the Calibration Values register (Addr: 5h). The register values are R0, R1, R2... R239 where R0 is a dummy value. The contents of R<239:1> should be stored.

4. Set SSC (Addr: 4h, Bit 7) to 0.

5. Continue with normal operation.

To write calibration values to the SPI, do the following:

1. Set ADC to operating conditions at which Calibration Values were previously read.

2. Set SSC (Addr: 4h, Bit 7) to 1.

3. Write exactly 239 times the Calibration Values register (Addr: 5h). The registers should be written R1, R2, ... , R239.

4. Make two additional dummy writes of 0000h.

5. Set SSC (Addr: 4h, Bit 7) to 0.

6. Continue with normal operation.

5.3.3.7 Calibration and Power-Down

If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC12D1800RF will immediately power down. The calibration cycle will continue when either or both channels are powered back up, but the calibration will be compromised due to the incomplete settling of bias currents directly after power up. Therefore, a new calibration should be executed upon powering the ADC12D1800RF back up. In general, the ADC12D1800RF should be recalibrated when either or both channels are powered back up, or after one channel is powered down. For best results, this should be done after the device has stabilized to its operating temperature.

5.3.3.8 Calibration and the Digital Outputs

During calibration, the digital outputs (including DI, DId, DQ, DQd and OR) are set logic-low, to reduce noise. The DCLK runs continuously during calibration. After the calibration is completed and the CalRun signal is logic-low, it takes an additional 60 Sampling Clock cycles before the output of the ADC12D1800RF is valid converted data from the analog inputs. This is the time it takes for the pipeline to flush, as well as for other internal processes.

Table 5-5 Supported Demux, Data Rate Modes

5.5.1.1 Non-Extended Control Mode

In Non-extended Control Mode (Non-ECM), the Serial Interface is not active and all available functions are controlled via various pin settings. Non-ECM is selected by setting the ECE Pin to logic-high. Note that, for the control pins, "logic-high" and "logic-low" refer to V_A and GND, respectively. Nine dedicated control pins provide a wide range of control for the ADC12D1800RF and facilitate its operation. These control pins provide DES Mode selection, Demux Mode selection, DDR Phase selection, execute Calibration, Calibration Delay setting, Power Down I-channel, Power Down Q-channel, Test Pattern Mode selection, and Full-Scale Input Range selection. In addition to this, two dual-purpose control pins provide for AC/DC-coupled Mode selection and LVDS output common-mode voltage selection. See Table 5-6 for a summary.

5.5.1.2 Extended Control Mode

In Extended Control Mode (ECM), most functions are controlled via the Serial Interface. In addition to this, several of the control pins remain active. See Table 5-1 for details. ECM is selected by setting the ECE Pin to logic-low. If the ECE Pin is set to logic-high (Non-ECM), then the registers are reset to their default values. So, a simple way to reset the registers is by toggling the ECE pin. Four pins on the ADC12D1800RF control the Serial Interface: SCS, SCLK, SDI and SDO. This section covers the Serial Interface. The Register Definitions are located at the end of the datasheet so that they are easy to find, see Section 5.6.1.

5.5.1.2.1 The Serial Interface

The ADC12D1800RF offers a Serial Interface that allows access to the sixteen control registers within the device. The Serial Interface is a generic 4-wire (optionally 3-wire) synchronous interface that is compatible with SPI type interfaces that are used on many micro-controllers and DSP controllers. Each serial interface access cycle is exactly 24 bits long. A register-read or register-write can be accomplished in one cycle. The signals are defined in such a way that the user can opt to simply join SDI and SDO signals in his system to accomplish a single, bidirectional SDI/O signal. A summary of the pins for this interface may be found in Table 5-7. See Figure 4-8 for the timing diagram and Section 4.14 for timing specification details. Control register contents are retained when the device is put into power-down mode. If this feature is unused, the SCLK, SDI, and SCS pins may be left floating because they each have an internal pull-up.

Table 5-7 Serial Interface Pins

Pin	Name
C4	SCS (Serial Chip Select bar)
C5	SCLK (Serial Clock)
B4	SDI (Serial Data In)
A3	SDO (Serial Data Out)

SCS: Each assertion (logic-low) of this signal starts a new register access, i.e. the SDI command field must be ready on the following SCLK rising edge. The user is required to de-assert this signal after the 24th clock. If the SCS is de-asserted before the 24th clock, no data read / write will occur. For a read operation, if the SCS is asserted longer than 24 clocks, the SDO output will hold the D0 bit until SCS is de-asserted. For a write operation, if the SCS is asserted longer than 24 clocks, data write will occur normally through the SDI input upon the 24th clock. Setup and hold times, t_SCS and t_HCS, with respect to the SCLK must be observed. SCS must be toggled in between register access cycles.

SCLK: This signal is used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the falling edge. The user may disable the clock and hold it at logic-low. There is no minimum frequency requirement for SCLK; see f_SCLK in Section 4.14 for more details.

SDI: Each register access requires a specific 24-bit pattern at this input, consisting of a command field and a data field. If the SDI and SDO wired are shared (3-wire mode), then during read operations it is necessary to tri-state the master which is driving SDI while the data field is being output by the ADC on SDO. The master must be at TRI-STATE before the falling edge of the 8th clock. If SDI and SDO are not shared (4-wire mode), then this is not necessary. Setup and hold times, t_SH and t_SSU, with respect to the SCLK must be observed.

SDO: This output is normally at TRI-STATE and is driven only when SCS is asserted, the first 8 bits of command data have been received and it is a READ operation. The data is shifted out, MSB first, starting with the 8th clock's falling edge. At the end of the access, when SCS is de-asserted, this output is at TRI-STATE once again. If an invalid address is accessed, the data sourced will consist of all zeroes. If it is a read operation, there will be a bus turnaround time, t_BSU, from when the last bit of the command field was read in until the first bit of the data field is written out.

Table 5-8 shows the Serial Interface bit definitions.

Table 5-8 Command and Data Field Definitions⁽¹⁾

Bit No.	Name	Comments
1	Read / Write (R/W)	1b indicates a read operation 0b indicates a write operation
2-3	Reserved	Bits must be set to 10b
4-7	A<3:0>	16 registers may be addressed. The order is MSB first
8	X	This is a "don't care" bit
9-24	D<15:0>	Data written to or read from addressed register

(1) The serial data protocol is shown for a read and write operation in Figure 5-5 and Figure 5-6, respectively.

Figure 5-5 Serial Data Protocol - Read Operation

Figure 5-6 Serial Data Protocol - Write Operation

Table 5-9 Register Addresses

Table 5-10 Configuration Register 1

Table 5-11 Reserved

Table 5-12 I-channel Offset Adjust

Table 5-13 I-channel Full Scale Range Adjust

Table 5-14 Calibration Adjust⁽¹⁾

Table 5-15 Calibration Values⁽¹⁾

Table 5-16 Bias Adjust

Table 5-17 DES Timing Adjust

Table 5-18 Reserved

Table 5-19 Reserved

Table 5-20 Q-channel Offset Adjust

Table 5-21 Q-channel Full-Scale Range Adjust

Table 5-22 Aperture Delay Coarse Adjust

Table 5-23 Aperture Delay Fine Adjust⁽¹⁾

Table 5-24 AutoSync

Table 5-25 Reserved