SLOS729D October 2011 – November 2015 AFE5808A
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Description (continued)
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 ADC Register Map
- 8.6.2
ADC Register/Digital Processing Description
- 8.6.2.1 AVERAGING_ENABLE: Address: 2[11]
- 8.6.2.2 ADC_OUTPUT_FORMAT: Address: 4[3]
- 8.6.2.3 DIGITAL_GAIN_ENABLE: Address: 3[12]
- 8.6.2.4 DIGITAL_HPF_ENABLE
- 8.6.2.5 DIGITAL_HPF_FILTER_K_CHX
- 8.6.2.6 LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
- 8.6.2.7 LVDS_OUTPUT_RATE_2X: Address: 1[14]
- 8.6.2.8 CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
- 8.6.2.9 SERIALIZED_DATA_RATE: Address: 3[14:13]
- 8.6.2.10 TEST_PATTERN_MODES: Address: 2[15:13]
- 8.6.2.11 SYNC_PATTERN: Address: 10[8]
- 8.6.3 VCA Register Map
- 8.6.4 AFE5808A VCA Register Description
-
9 Application and Implementation
- 9.1 Application Information
- 9.2 Typical Application
- 9.3
Do's and Don'ts
- 9.3.1 Driving the Inputs (Analog or Digital) Beyond the Power-Supply Rails
- 9.3.2 Driving the Device Signal Input With an Excessively High Level Signal
- 9.3.3 Driving the VCNTL Signal With an Excessive Noise Source
- 9.3.4 Using a Clock Source With Excessive Jitter, an Excessively Long Input Clock Signal Trace, or Having Other Signals Coupled to the ADC or CW Clock Signal Trace
- 9.3.5 LVDS Routing Length Mismatch
- 9.3.6 Failure to Provide Adequate Heat Removal
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- ZCF|135
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
6 Pin Configuration and Functions
Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ACT1...ACT8 | B9~ B2 | I | Active termination input pins for CH1~8. 1-μF capacitors are recommended. See the Application and Implementation section. |
| AVDD | A1, D8, D9, E8, E9, K1 | Supply | 3.3-V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks |
| AVDD_5V | K2 | Supply | 5-V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks |
| AVDD_ADC | J6, J7, K8, L3, M1, M2 |
Supply | 1.8-V Analog power supply for ADC |
| AVSS | C1, D1~D7, E3~E7, F3~F7, G1~G7, H3~H7,J3~J5, K6 | — | Analog ground |
| CLKM_ADC | L2 | I | Negative input of differential ADC clock. In the single-end clock mode, it can be tied to GND directly or through a 0.1-µF capacitor. |
| CLKP_ADC | L1 | I | Positive input of differential ADC clock. In the single-end clock mode, it can be tied to clock signal directly or through a 0.1-µF capacitor. |
| CLKM_16X | F9 | I | Negative input of differential CW 16X clock. Tie to GND when the CMOS clock mode is enabled. In the 4X and 8X CW clock modes, this pin becomes the 4X or 8X CLKM input. In the 1X CW clock mode, this pin becomes the in-phase 1X CLKM for the CW mixer. Can be floated if CW mode is not used. |
| CLKP_16X | F8 | I | Positive input of differential CW 16X clock. In 4X and 8X clock modes, this pin becomes the 4X or 8X CLKP input. In the 1X CW clock mode, this pin becomes the in-phase 1X CLKP for the CW mixer. Can be floated if CW mode is not used. |
| CLKM_1X | G9 | I | Negative input of differential CW 1X clock. Tie to GND when the CMOS clock mode is enabled (Refer to Figure 88 for details). In the 1X clock mode, this pin is the quadrature-phase 1X CLKM for the CW mixer. Can be floated if CW mode is not used. |
| CLKP_1X | G8 | I | Positive input of differential CW 1X clock. In the 1X clock mode, this pin is the quadrature-phase 1X CLKP for the CW mixer. Can be floated if CW mode is not used. |
| CM_BYP | B1 | Bias | Bias voltage and bypass to ground. ≥ 1 µF is recommended. To suppress the ultra low frequency noise, 10 µF can be used. |
| CW_IP_AMPINM | E2 | O | Negative differential input of the In-phase summing amplifier. External LPF capacitor has to be connected between CW_IP_AMPINM and CW_IP_OUTP. This pin becomes the CH7 PGA negative output when PGA test mode is enabled. Can be floated if not used. |
| CW_IP_AMPINP | E1 | O | Positive differential input of the In-phase summing amplifier. External LPF capacitor has to be connected between CW_IP_AMPINP and CW_IP_OUTM. This pin becomes the CH7 PGA positive output when PGA test mode is enabled. Can be floated if not used. |
| CW_IP_OUTM | F1 | O | Negative differential output for the In-phase summing amplifier. External LPF capacitor has to be connected between CW_IP_AMPINP andCW_IP_OUTPM. Can be floated if not used. |
| CW_IP_OUTP | F2 | O | Positive differential output for the In-phase summing amplifier. External LPF capacitor has to be connected between CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used. |
| CW_QP_AMPINM | J2 | O | Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be connected between CW_QP_AMPINM and CW_QP_OUTP. This pin becomes CH8 PGA negative output when PGA test mode is enabled. Can be floated if not used. |
| CW_QP_AMPINP | J1 | O | Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be connected between CW_QP_AMPINP and CW_QP_OUTM. This pin becomes CH8 PGA positive output when PGA test mode is enabled. Can be floated if not used. |
| CW_QP_OUTM | H1 | O | Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor has to be connected between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used. |
| CW_QP_OUTP | H2 | O | Positive differential output for the quadrature-phase summing amplifier. External LPF capacitor has to be connected between CW_QP_AMPINM and CW_QP_OUTP. Can be floated if not used. |
| D1M~D8M | N8, P9~P7, P3~P1, N2 | O | ADC CH1~8 LVDS negative outputs |
| D1P~D8P | N9, R9~R7, R3~R1, N1 | O | ADC CH1~8 LVDS positive outputs |
| DCLKM | P6 | O | LVDS bit clock (7x) negative output |
| DCLKP | R6 | O | LVDS bit clock (7x) positive output |
| DNC | K7, L5~L7,M5~M8, N4, N6 | — | Do not connect. Must leave floated. |
| DVDD | N3, N7 | Supply | ADC digital and I/O power supply, 1.8 V |
| DVSS | N5, P5, R5 | — | ADC digital ground |
| FCLKM | P4 | O | LVDS frame clock (1X) negative output |
| FCLKP | R4 | O | LVDS frame clock (1X) positive output |
| INM1…INM8 | C9~C2 | I | CH1~8 complimentary analog inputs. Bypass to ground with ≥ 0.015-µF capacitors. The HPF response of the LNA depends on the capacitors. |
| INP1...INP8 | A9~A2 | I | CH1~8 analog inputs. AC couple to inputs with ≥ 0.1-µF capacitors. |
| PDN_ADC | L8 | I | ADC partial (fast) power down control pin with an internal pull down resistor of 100 kΩ. Active High. Either 1.8-V or 3.3-V logic level can be used. |
| PDN_VCA | J8 | I | VCA partial (fast) power down control pin with an internal pull down resistor of 20 kΩ. Active High. 3.3-V logic level is recommended. |
| PDN_GLOBAL | H8 | I | Global (complete) power-down control pin for the entire chip with an internal pull down resistor of 20 kΩ. Active High. 3.3-V logic level is recommended. |
| REFM | L4 | — | 0.5-V reference output in the internal reference mode. Must leave floated in the internal reference mode. Adding test point on PCB is recommended for monitoring the reference output. |
| REFP | M4 | — | 1.5-V reference output in the internal reference mode. Must leave floated in the internal reference mode. Adding test point on PCB is recommended for monitoring the reference output. |
| RESET | H9 | I | Hardware reset pin with an internal pull-down resistor of 20 kΩ. Active high, 3.3-V logic level is recommended. |
| SCLK | J9 | I | Serial interface clock input with an internal pull-down resistor of 20 kΩ, 3.3-V logic level is recommended. |
| SDATA | K9 | I | Serial interface data input with an internal pull-down resistor of 20 kΩ, 3.3-V logic level is recommended. |
| SDOUT | M9 | O | Serial interface data readout. High impedance when readout is disabled, 1.8-V logic |
| SEN | L9 | I | Serial interface enable with an internal pull up resistor of 20 kΩ. Active low, 3.3-V logic level is recommended. |
| VCNTLM | K4 | I | Negative differential attenuation control pin. Common mode voltage is 0.75V. |
| VCNTLP | K3 | I | Positive differential attenuation control pin. Common mode voltage is 0.75V. |
| VHIGH | K5 | Bias | Bias voltage; bypass to ground with ≥ 1 µF. |
| VREF_IN | M3 | Bias | ADC 1.4-V reference input in the external reference mode; bypass to ground with 0.1 µF. |
| DNC | K7, L5~L7, M5~M8, N4, N6 | — | Do not connect. Must leave floated. |