SLUSBD1B MARCH 2013 – September 2016
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Function
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Switching Frequency Adjust
- 6.3.2 High Accuracy Current Sense Amplifiers
- 6.3.3 Charger Timeout
- 6.3.4 Input Over-Current Protection (ACOC)
- 6.3.5 Converter Over-Current Protection
- 6.3.6 Battery Over-Voltage Protection (BATOVP)
- 6.3.7 System Over-Voltage Protection (SYSOVP)
- 6.3.8 Thermal Shutdown Protection (TSHUT)
- 6.3.9 Adapter Over-Voltage Protection (ACOVP)
- 6.3.10 Adapter Detect and ACOK Output
- 6.3.11 ACFET/RBFET Control
- 6.3.12 DPM
- 6.3.13 Buck Converter Power up
- 6.4 Device Functional Modes
- 6.5 Programming
- 7 Application and Implementation
- 8 Power Supply Recommendations
- 9 Layout
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGR|20
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGR|20
訂購信息
6 Detailed Description
6.1 Overview
The bq24715 is a 2-3 cell battery charge controller with power selection for multi-chemistry portable applications such as notebook and ultrabook. It supports wide input range of input sources from 6 V to 24 V, and 2-3 cell battery.
The bq24715 supports automatic system power source selection with separate drivers for n-channel MOSFETs on the adapter side, and p-channel MOSFETs on the battery side.
The bq24715 features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter overloading. During battery charging, as the system power increases, the charging current will reduce to maintain total input current below adapter rating. If system power demand is temporarily exceeds adapter rating, the bq24715 supports NVDC architecture to allow battery discharge energy to supplement system power
The SMBus controls input current, charge current and charge voltage registers with high resolution, high accuracy regulation limits.
6.2 Functional Block Diagram
6.3 Feature Description
6.3.1 Switching Frequency Adjust
The charger switching frequency can be adjusted ±25% to solve EMI issue via SMBus command. ChargeOption() bit [9:8] can be used to set switching frequency.
If frequency is reduced, the current ripple is increased. Inductor value must be carefully selected so that it will not trigger cycle-by-cycle peak over current protection even for the worst condition such as higher input voltage, 50% duty cycle, lower inductance and lower switching frequency.
6.3.2 High Accuracy Current Sense Amplifiers
If LOWPOWER bit is zero (ChargeOption() bit[15] = 0), as an industry standard, high accuracy current sense amplifiers (CSA) are used to monitor the input current or the discharge current, selectable via SMBUS, see Table 3. Once VCC is above UVLO and ACDET is above 0.6V, input current CSA turns on and the IOUT output becomes valid. Once SRN is above UVLO and ChargeOption() bit[15] = 0, discharge current CSA turns on and the IOUT output becomes valid. The CSA senses voltage across the input sense resistor by a factor of 40 or across the output sense resistor by a factor of 16 through the IOUT pin. To lower the voltage on current monitoring, a resistor divider from IOUT to GND can be used and accuracy over temperature can still be achieved.
If LOWPOWER bit is "1" (ChargeOption() bit[15] = 1) and only a valid battery (BAT>UVLO) is connected to system with an input adaptor (ACDET<0.6V or VCC<UVLO), the IC enter low quiescent current mode, all current monitoring circuits are turned off.
A 100pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay.
6.3.3 Charger Timeout
The bq24715 includes a watchdog timer to terminate charging if the charger does not receive a write ChargeVoltage() or write ChargeCurrent() command within 175s (adjustable via ChargeOption() command). If a watchdog timeout occurs all register values keep unchanged but charge is suspended. Write ChargeVoltage() or write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. The watchdog timer can be disabled, or set to 44s, 88s or 175s via SMBus command (ChargeOption() bit[14:13]). If watchdog is in timeout, disabling watchdog timer by writing ChargeOption() bit[14:13] also resumes charging.
6.3.4 Input Over-Current Protection (ACOC)
If the input current exceeds the 3.33X of input current DAC set point, ACFET/RBFET is turned-off and charge is disabled. After 300ms, ACFET/RBFET will be turned on again.
The ACOC function threshold can be set to 3.33X of input DPM current (ChargeOption() bit [7]=1) or function disable(ChargeOption() bit [7]=0, default) via SMBus command
The bq24715 has a cycle-to-cycle peak over-current protection. It monitors the voltage across Rds_on of the LSFET or the input current sense resistor, and prevents the converter from over current condition. The high-side gate drive turns off when the over-current is detected, and resumes automatically when the over-current condition is gone.
6.3.5 Converter Over-Current Protection
When LODRV pulse is longer than 100ns blanking time, the LSFET OCP is active and the threshold is automatically set to 350mV (ChargeOption() bit [6]=1, default) or 250mV (ChargeOption() bit [6]=0) via SMBus command. The blanking time prevents noise when MOSFET just turn on.
When LODRV pulse is shorter than 100ns blanking time, bq24715 uses 2.5 times of InputCurrent() setting (minimum 45mV) as Vacp-acn protection threshold to turn off the high-side gate drive even the IDPM function is disabled (0x12[1]=0). Please set InputCurrent() to a right value even IDPM is disabled.
6.3.6 Battery Over-Voltage Protection (BATOVP)
The bq24715 will not allow the BATFET to turn-on when the battery voltage at SRN exceeds 104% of the regulation voltage set-point. This allows quick response to an over-voltage condition – such as occurs when the load is removed or the battery is disconnected. A 4mA current sink from SRP to GND is on only during BATOVP and allows discharging the stored output inductor energy that is transferred to the output capacitors.
6.3.7 System Over-Voltage Protection (SYSOVP)
When system voltage is higher than maximum allowed voltage (VSYSOVP_RISE), it is considered as system overvoltage. If SYSOVP is detected, it will latch off ACFET, RBFET, and buck converter to prevent any potential damage to the system due to unexpected short (e.g. high HFET short) or other conditions. Reading chargeoption bit[11]=1 reflect this latch-off protection and writing chargeoption bit[11]=0 clear the latch. Adapter replug-in can also clear the latch.
6.3.8 Thermal Shutdown Protection (TSHUT)
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off for self-protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction temperature falls below 135°C. During thermal shut down, the REGN LDO current limit is reduced to 16mA. Once the temperature falls below 135°C, charge can be resumed with soft start.
6.3.9 Adapter Over-Voltage Protection (ACOVP)
The bq24715 uses a fixed ACOVP voltage (26V typ). When VCC pin voltage is higher than VACOVP, it is considered as adapter over voltage. ACOK will be pulled low, and charge will be disabled. ACFET will be turned off to disconnect high voltage adapter during ACOVP. BATFET will be turned on if turn-on conditions are valid. See the “ACFET/RBFET and BATFET Control” sections for detail.
When VCC pin voltage falls below 24V and ACDET above 2.4V, it is considered as adapter voltage returns back to normal voltage. ACOK will be pulled high by external pull up resistor. ACFET and RBFET will be turned on to power the converter from adapter.
6.3.10 Adapter Detect and ACOK Output
The bq24715 uses an ACOK comparator to determine the present of adapter on VCC pin. An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The VACOK_RISE threshold should make the adapter voltage greater than the maximum battery voltage plus VCC_SRN (sleep) comparator rising threshold, but lower than the maximum allowed VACOVP voltage.
The open drain ACOK output requires external pull up resistor to system digital rail for a high level. It can be pulled to external rail under the following conditions:
- VACOVP > VVCC > UVLO;
- VACDET > 2.4V
- VVCC-VSRN > 675mV (not in sleep mode);
6.3.11 ACFET/RBFET Control
The ACDRV drives a pair of common-source (CMSRC) n-channel power MOSFETs (ACFET: Q1A and RBFET: Q1B) between adapter and converter. The ACFET separates adapter from converter, and provides a limited di/dt when plugging in adapter by controlling the ACFET turn-on time. The RBFET provides battery discharge protection when adapter voltage is lower than battery, and minimizes system power dissipation with its low RDS(on) compared to a Schottky diode.
When adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off. And BATFET is turned on to discharge battery. After adapter is detected (ACDET pin voltage higher than 2.4V), adapter begins to provide power to system.
The gate drive voltage on ACFET and RBFET is VCMSRC+6V. If the ACFET and RBFET have been turned on for 20ms, and the voltage across ACDRV and CMSRC is still 0.2V below VACFET, ACFET and RBFET will be turned off.
To limit the in-rush current on ACDRV pin and CMSRC pin, a 4kΩ resistor is recommended on each of the three pins.
To limit the adapter inrush current when ACFET is turned on to provide power converter from adapter, the external Cgs and Cgd capacitor of ACFET must be carefully selected. The larger the Cgs and Cgd capacitance, the slower turn on of ACFET will be and less inrush current of adapter. However, if Cgs and Cgd is too large, the ACDRV-CMSRC voltage may still be low after 20ms turn on time window is expired. To make sure ACFET will not be turned on when adapter is hot plug in, the Cgs value should be 20 times or higher of Cgd.
6.3.12 DPM
When the input current exceeds the input current limit setting and IPM_EN is enabled (ChargeOption() bit [1]=1), the bq24715 decreases the charge current to provide priority to system load current. As the system current rises, the available charge current drops linearly to zero. Higher systems loads can be drawn from the battery, battery discharges and BATFET is turned on when discharge current is higher than 256mA.
To reduce the risk for overcharging battery at battery insertion, please disable charge if the battery is absent.
6.3.13 Buck Converter Power up
After the ACFET is turned on, the converter is enabled and the HSFET and LSFET start switching. Every time the buck converter is started, the IC automatically applies soft-start (no soft-start when exit LEARN) on buck output current to avoid any overshoot or stress on the output capacitors or the power converter. The buck output current starts at 128mA, and the step size is 64mA in CCM mode for a 10mΩ current sensing resistor. Each step lasts around 24µs in CCM mode, until it reaches the programmed charge current limit. No external components are needed for this function.
When power up, converter output voltage is default value set by CELL pin configuration. After converter starts switching about 100ms, CELL pin setting is locked. If CELL pin is pulled to LOW when power-up, converter output is default 2S for bq24715.
6.4 Device Functional Modes
6.4.1 LDO Mode and Minimum System Voltage
The BATDRV drives a p-channel BATFET between converter output (system node) and battery to provide a charge and discharge path for battery. When battery voltage is below the minimum system voltage setting, this BATFET works in linear mode as LDO (default chargeoption() bit[2]=1, the precharge current is set by ChargeCurrent() and clamped below 384mA) thus to keep system node voltage always higher than the minimum system voltage setting. If battery voltage reaches the minimum system voltage, BATFET fully turns on. This LDO function can be optionally disabled by set "LDO Mode Enable" bit low (chargeoption() bit[2]=0) and BATFET is fully turned on. At this condition, the battery pack internal circuit will maintain battery terminal voltage higher than system minimum voltage. And the precharge current also determined by battery pack internal circuit.
Figure 6. ChargeOption[2] (LDO Mode)
6.4.2 PWM Mode Converter Operation
The synchronous buck PWM converter uses a fixed frequency voltage control scheme and internal type III compensation network. The LC output filter gives a characteristic resonant frequency
The resonant frequency fo is used to determine the compensation to ensure there is sufficient phase margin for the target bandwidth. Suggested component value as charge current of 800Hz default switching frequency is shown in Table 8.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point.
Table 1. Suggested Component Value as Output Current of Default 800-kHz Switching Frequency
| Component | Recommended Value |
|---|---|
| Output Inductor Lo (µH) | 3.3 or 2.2 |
| System node capacitor (µF) | 47- 350(1) |
| SRN node Capacitor Co (µF) | 0.1-1 |
| Sense Resistor (mΩ) | 10 |
The bq24715 has four loops of regulation: input current, charge current, charge voltage and minimum system voltage. The four loops are brought together internally at the error amplifier. The maximum voltage of the four loops appears at the output of the error amplifier EAO. An internal saw-tooth ramp is compared to the internal error control signal EAO to vary the duty-cycle of the converter.
When the battery charge voltage approaches the input voltage, EAO signal is allowed to exceed the saw-tooth ramp peak in order to get a 100% duty-cycle. If voltage across BTST and PHASE pins falls below VBTST_REFRESH, a refresh cycle starts and low-side n-channel power MOSFET is turned on to recharge the BTST capacitor. It can achieve duty cycle of up to 99.5% with pulse skip.
6.4.3 Continuous Conduction Mode (CCM)
With sufficient charge current, the inductor current never crosses zero, which is defined as Continuous Conduction Mode. The controller starts a new cycle with ramp coming up from 200mV. As long as EAO voltage is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of each switching cycle, ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the low-side power MOSFET conducts the inductor current.
During CCM mode, the inductor current is always flowing and creates a fixed two-pole system. Having the LSFET turn-on keeps the power dissipation low, and allows safely at high output currents.
6.4.4 Discontinuous Conduction Mode (DCM)
When LSFET is turned on, the inductor current will decrease. If this current goes to zero, the converter enters Discontinuous Conduction Mode. Every cycle, when the voltage across ACP and ACN falls below 1.25mV (125mA on 10mΩ), the light-load comparator turns off LSFET to avoid negative inductor current, which may boost the system via the body diode of HSFET. There is also a cycle-by-cycle converter under-current comparator monitor the LFET current and prevent it goes negative.
During the DCM mode the loop response automatically changes. It changes to a single pole system and the pole is proportional to the load current.
6.4.5 PFM Mode
In order to improve converter light-load efficiency, the bq24715 switches to PFM control at light load with charge disable or charge in LDO mode. The effective switching frequency will decrease accordingly when system load decreases. The minimum frequency can be limit to 40kHz if set IDPM_EN bit high (ChargeOption() bit[10]=1). To have higher light load efficiency, set "Audio Frequency Limit" bit low (Chargeoption() bit[10]=0, default).
6.4.6 Learn Mode
A battery LEARN cycle can be activated via SMBus "LEARN Enable" command (ChargeOption() bit[5]=1 enable Learn Mode). When LEARN is enabled with an adapter connected, the system power switch to battery by turning off converter and keep ACFET/BATFET on. Learn mode allows the battery to discharge in order to calibrate the battery gas gauge over a complete discharge/charge cycle. When LEARN is disabled, the system power switch to adapter by turning on converter in a few hundreds µs.
The bq24715 also supports hardware pin to exist LEARN mode by pulling CELL to GND. When Cell pin is pulled to GND,bq24715 resets "LEARN Enable" (ChargeOption() bit[5]) and IDPM_EN (ChargeOption() bit[1]), and reset chargevoltage() and chargecurrent().
6.4.7 IDPM Disable at Battery Removal
CELL pull to GND can also be used to disable IDPM function automatically when battery is removed.
When battery present, IOUT monitors discharge current and CPU can do throttling when IOUT is higher than battery discharge limit.
When battery is removed, CELL is pulled to GND. IC disables input DPM function and switch IOUT to monitor input current, thus CPU throttling when IOUT higher than limit.
After insert battery back, EC need set bit[1]=1 to enable IDPM function.
- Customer who has external discharge current monitor can set "FIX IOUT" ChargeOption() bit[3]=1 and "IOUT Selection" ChargeOption() bit[4]=0 to have fixed IOUT monitoring adapter current.
- Customer who has external adapter current monitor can set "FIX IOUT" ChargeOption() bit[3]=1 and "IOUT Selection" ChargeOption() bit[4]=1 to have fixed IOUT monitoring discharge current.
6.5 Programming
6.5.1 SMBus Communication
6.5.1.1 SMBus Interface
The bq24715 supports SMBus communication interface. Gas gauge broadcasting mode is supported.
The bq24715 operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The device uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24715 uses the SMBus Read-Word and Write-Word protocols (Figure 7) to communicate with the smart battery. The bq24715 performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the device has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).
SMBus communication is enabled with the following conditions:
- VVCC or VSRN is above UVLO;
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pull-up resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a START condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 2 and Figure 3 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24715 because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24715 supports the charger commands as described in Table 2.
6.5.1.1.1 Write-Word Format
| S | SLAVE ADDRESS | W | ACK | COMMAND BYTE | ACK | LOW DATA BYTE | ACK | HIGH DATA BYTE | ACK | P |
| 7 BITS | 1b | 1b | 8 BITS | 1b | 8 BITS | 1b | 8 BITS | 1b | ||
| MSB m LSB | 0 | 0 | MSB m LSB | 0 | MSB m LSB | 0 | MSB m LSB | 0 |
| Preset to 0b0001001 | ChargeCurrent() = 0x14H
ChargeVoltage() = 0x15H InputCurrent() = 0x3FH MinSysVoltage() = 0x3EH ChargeOption() = 0x12H |
D7 m | D0 | D15mD0 | ||||||
6.5.1.1.2 Read-Word Format
| S | SLAVE ADDRESS | W | ACK | COMMAND BYTE | ACK | S | SLAVE ADDRESS | R | ACK | LOW DATA BYTE | ACK | HIGH DATA BYTE | NACK | P |
| 7 BITS | 1b | 1b | 8 BITS | 1b | 8 BITS | 1b | 1b | 8 BITS | 1b | 8 BITS | 1b | |||
| MSB m LSB | 0 | 0 | MSB m LSB | 0 | MSB m LSB | 1 | 0 | MSB m LSB | 0 | MSB m LSB | 1 |
| Preset to 0b0001001 | DeviceID() = 0xFFH
ManufactureID() = 0xFEH ChargeCurrent() = 0x14H ChargeVoltage() = 0x15H InputCurrent() = 0x3FH MinSysVoltage() = 0x3EH ChargeOption() = 0x12H |
Preset to 0b0001001 | D7mD0 | D15mD0 | ||||||||||
| LEGEND: | |
| S = START CONDITION OR REPEATED START CONDITION | P = STOP CONDITION |
| ACK = ACKNOWLEDGE (LOGIC-LOW) | NACK = NOT ACKNOWLEDGE (LOGIC-HIGH) |
| W = WRITE BIT (LOGIC-LOW) | R = READ BIT (LOGIC-HIGH) |
| MASTER TO SLAVE | ||
| SLAVE TO MASTER | ||
6.5.1.2 SMBus Commands
The bq24715 supports seven battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24715. The ManufacturerID() command always returns 0x0040H and the DeviceID() command always returns 0x0010H.
Table 2. Battery Charger Command Summary
6.5.1.3 Setting Charger Options
By writing ChargeOption() command (0x12H or 0b00010010), bq24715 allows users to change several charger options after POR (Power On Reset) as shown in Table 3.
Table 3. Charge Options Register (0x12H)
| BIT | BIT NAME | DESCRIPTION |
|---|---|---|
| [15] | LOWPOWER | Effective on BAT power only (ACDET<0.6 or VCC<UVLO) 0: turn on discharge current monitoring 1: lower quiescent current, discharge current monitoring are turned off <default @ POR> |
| [14:13] | WATCHDOG Timer Adjust | Set maximum delay between consecutive SMBus Write charge voltage or charge current command. The charge will be suspended if IC does not receive write charge voltage or write charge current command within the watchdog time period and watchdog timer is enabled. The charge will be resumed after receive write charge voltage or write charge current command when watchdog timer expires and charge suspends. 00: Disable Watchdog Timer 01: Enabled, 44 sec 10: Enabled, 88 sec 11: Enable Watchdog Timer (175s) <default @ POR> |
| [12] | SYSOVP | Converter latch-off when sysovp is detected.
0: 15.1 V for 3s; 10.1 V for 2s <default @ POR> 1: 17.0 V for 3s, 11.3 V for 2s |
| [11] | SYSOVP status& clear | 0: not OVP (default; write 0 to clear the OVP status)
1: OVP latch (read only) |
| [10] | Audio Frequency Limit | 0: No limit of switching frequency <default @ POR>
1: Set minimum switching frequency to 40 kHz to avoid audio noise |
| [9:8] | Switching Frequency Setting | 00:600kHz 01:800kHz <default @ POR> 10: 1MHz 11: 800 kHz |
| [7] | ACOC setting | ACOC protection threshold by detecting the ACP_ACN voltage. 0: function is disable <default @ POR> 1: 333% IDPM |
| [6] | LSFET OCP threshold | When LSFET is ON, check the Rdson voltage drop, limit the current cycle-by-cycle 0: 250mV 1: 350mV <default> |
| [5] | LEARN Enable | IC turns off buck converter (ACFET and RBFET still on), and turns on BATFET to support battery discharge mode. Set this bit 0 will stop LEARN mode and turn on buck converter back. Can be used to support battery LEARN mode 0: Disable LEARN Mode <default @ POR> 1: Enable LEARN Mode |
| [4] | IOUT Selection | When bit[3]=1, bit[4] serve as input MM 0: IOUT is the 40x adapter current amplifier output MM 1: IOUT is the 16x discharge current amplifier output When bit[3]=0, bit[4] serve as output (indicate IOUT selection) MM 0: IOUT the 40x adapter current amplifier output; when IDPM is disabled <default @ POR> MM 1: IOUT is the 16x discharge current amplifier output; when IDPM is enabled |
| [3] | FIX IOUT | 0: switch IOUT based on IDPM_EN <default @ POR>
1: select IOUT based on bit[4] |
| [2] | LDO Mode Enable | 0: Disable LDO mode. BATFET ON. Precharge current is set by battery pack LDO. 1: Enable LDO mode - Precharge current is set by ChargeCurrent() and clamped below 384mA <default@POR> |
| [1] | IDPM_EN | 0: Disable <default @ POR>
1: Enable |
| [0] | Charge Inhibit | 0: Enable Charge <default @ POR>
1: Inhibit Charge |
6.5.1.4 Setting the Charge Current
To set the charge current, write a 16bit ChargeCurrent() command (0x14H or 0b00010100) using the data format listed in Table 6. With 10mΩ sense resistor, the bq24715 provides a charge current range of 128mA to 8.128A, with 64mA step resolution. Sending ChargeCurrent() below 64mA clears the register and terminates charging. Upon POR, charge current is 0 A. A 0.1-µF capacitor between SRP and SRN for differential mode filtering is recommended, 0.1µF capacitor between SRN and ground for common mode filtering, and an optional 0.1µF capacitor between SRP and ground for common mode filtering.
The SRP and SRN pins are used to sense RSNS with default value of 10mΩ. However, resistors of other values can also be used. For a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss.
Because writing valid 0x14H will enable charge, even if 0x15H is not changed (0x15H has default value at start-up). EC needs write 0x15H – (charge voltage) first, then write 0x14H – (charge current). After enable charge, IC will regulate the charge voltage and current at 0x14H and 0x15H setting to reduce the risk for overcharging battery. Also, please keep 0x14H register at zero if the battery is absent.
Table 4. Charge Current Register (0x14H), using 10-mΩ Sense Resistor
| BIT | BIT NAME | DESCRIPTION |
|---|---|---|
| 0 | — | Not used. |
| 1 | — | Not used. |
| 2 | — | Not used. |
| 3 | — | Not used. |
| 4 | — | Not used. |
| 5 | — | Not used. |
| 6 | Charge Current, DACICHG 0 | 0 = Adds 0mA of charger current. 1 = Adds 64mA of charger current. |
| 7 | Charge Current, DACICHG 1 | 0 = Adds 0mA of charger current. 1 = Adds 128mA of charger current. |
| 8 | Charge Current, DACICHG 2 | 0 = Adds 0mA of charger current. 1 = Adds 256mA of charger current. |
| 9 | Charge Current, DACICHG 3 | 0 = Adds 0mA of charger current. 1 = Adds 512mA of charger current. |
| 10 | Charge Current, DACICHG 4 | 0 = Adds 0mA of charger current. 1 = Adds 1024mA of charger current. |
| 11 | Charge Current, DACICHG 5 | 0 = Adds 0mA of charger current. 1 = Adds 2048mA of charger current. |
| 12 | Charge Current, DACICHG 6 | 0 = Adds 0mA of charger current. 1 = Adds 4096mA of charger current. |
| 13 | — | Not used. |
| 14 | — | Not used. |
| 15 | — | Not used. |
6.5.1.5 Setting the Max Charge Voltage
To set the output charge regulation voltage, write a 16bit MaxChargeVoltage() command (0x15H or 0b00010101) using the data format listed in Table 5. The bq24715 provides charge voltage range from 4.096 V to 9.6 V (2S setting) or 14.5 V (3S setting), with 16mV step resolution. Upon POR, Max charge voltage limit is 13.504 V for 3S setting (CELL=HIGH) or 9.008 V for 2S setting (CELL pin floating). Any value below 4.096 V results in default value.
If enable charge without writing any command to 0x15 register, the MaxChargeVoltage() is automatically changed to 8.4 V (2S setting) or 12.6 V (3S setting). If disable charge without writing any command to 0x15 register ever, the MaxChargeVoltage() automatically goes back to POR value. Once writing a valid number to 0x15 register, the MaxChargeVoltage() doesn't automatically change between enable charge and disable charge.
The SRN pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, and directly place a decoupling capacitor (0.1 µF recommended) as close to IC as possible to decouple high frequency noise.
Table 5. Max Charge Voltage Register (0x15H)
| BIT | BIT NAME | DESCRIPTION |
|---|---|---|
| 0 | — | Not used. |
| 1 | — | Not used. |
| 2 | — | Not used. |
| 3 | — | Not used. |
| 4 | Charge Voltage, DACV 0 | 0 = Adds 0mV of charger voltage. 1 = Adds 16mV of charger voltage. |
| 5 | Charge Voltage, DACV 1 | 0 = Adds 0mV of charger voltage. 1 = Adds 32mV of charger voltage. |
| 6 | Charge Voltage, DACV 2 | 0 = Adds 0mV of charger voltage. 1 = Adds 64mV of charger voltage. |
| 7 | Charge Voltage, DACV 3 | 0 = Adds 0mV of charger voltage. 1 = Adds 128mV of charger voltage. |
| 8 | Charge Voltage, DACV 4 | 0 = Adds 0mV of charger voltage. 1 = Adds 256mV of charger voltage. |
| 9 | Charge Voltage, DACV 5 | 0 = Adds 0mV of charger voltage. 1 = Adds 512mV of charger voltage. |
| 10 | Charge Voltage, DACV 6 | 0 = Adds 0mV of charger voltage. 1 = Adds 1024mV of charger voltage. |
| 11 | Charge Voltage, DACV 7 | 0 = Adds 0mV of charger voltage. 1 = Adds 2048mV of charger voltage. |
| 12 | Charge Voltage, DACV 8 | 0 = Adds 0mV of charger voltage. 1 = Adds 4096mV of charger voltage. |
| 13 | Charge Voltage, DACV 9 | 0 = Adds 0mV of charger voltage. 1 = Adds 8192mV of charger voltage. |
| 14 | Charge Voltage, DACV 9 | 0 = Adds 0mV of charger voltage. 1 = Adds 16384mV of charger voltage. |
| 15 | — | Not used. |
6.5.1.6 Setting the Minimum System Voltage
To set the minimum system voltage, write a 16bit MinSystemVoltage() command (0x3EH or 0b00111110) using the data format listed in Table 6. The bq24715 provides minimum system voltage range from 4.096 V up to maximum charge voltage, with 256 mV step resolution. Any MinSystemVoltage() below 4.096 V. Upon POR (set via CELL), charge voltage limit is 6.144 V for 2S setting and 9.216 V for 3S setting.
Table 6. Minimum System Voltage Register (0x3EH)
| BIT | BIT NAME | DESCRIPTION |
|---|---|---|
| 0 | — | Not used. |
| 1 | — | Not used. |
| 2 | — | Not used. |
| 3 | — | Not used. |
| 4 | — | Not used. |
| 5 | — | Not used. |
| 6 | — | Not used. |
| 7 | — | Not used. |
| 8 | Minimum System Voltage, DACMINSV 0 | 0 = Adds 0mV of system voltage. 1 = Adds 256mV of system voltage. |
| 9 | Minimum System Voltage, DACMINSV 1 | 0 = Adds 0mV of system voltage. 1 = Adds 512mV of system voltage. |
| 10 | Minimum System Voltage, DACMINSV 2 | 0 = Adds 0mV of system voltage. 1 = Adds 1024mV of system voltage. |
| 11 | Minimum System Voltage, DACMINSV 3 | 0 = Adds 0mV of system voltage. 1 = Adds 2048mV of system voltage. |
| 12 | Minimum System Voltage, DACMINSV 4 | 0 = Adds 0mV of system voltage. 1 = Adds 4096mV of system voltage. |
| 13 | Minimum System Voltage, DACMINSV 5 | 0 = Adds 0mV of system voltage. 1 = Adds 8192mV of system voltage. |
| 14 | — | Not used. |
| 15 | — | Not used. |
6.5.1.7 Setting Input Current
System current normally fluctuates as portions of the system are powered up or put to sleep. With the input current limit, the output current requirement of the AC wall adapter can be lowered, reducing system cost.
The total input current, from a wall cube or other DC source, is the sum of the system supply current and the current required by the charger. When the input current exceeds the set input current limit, the bq24715 decreases the charge current to provide priority to system load current. As the system current rises, the available charge current drops linearly to zero. Keep increasing the system current and the battery will run into supplement mode.
During DPM regulation, the total input current is the sum of the device supply current IBIAS, the charger input current, and the system load current ILOAD, and can be estimated as follows:
where η is the efficiency of the charger buck converter (typically 85% to 95%).
To set the input current limit, write a 16-bit InputCurrent() command (0x3FH or 0b00111111) using the data format listed in Table 7. When using a 10-mΩ sense resistor, the bq24715 provides an input-current limit range of 128 mA to 8.064 A, with 64 mA resolution. Sending InputCurrent() below 128 mA or above 8.064 A are ignored. Upon POR, default input current limit is 3.2 A.
The ACP and ACN pins are used to sense RAC with default value of 10 mΩ. However, resistors of other values can also be used. For a larger sense resistor, larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss.
Table 7. Input Current Register (0x3FH), Using 10-mΩ Sense Resistor
| BIT | BIT NAME | DESCRIPTION |
|---|---|---|
| 0 | — | Not used. |
| 1 | — | Not used. |
| 2 | — | Not used. |
| 3 | — | Not used. |
| 4 | — | Not used. |
| 5 | — | Not used. |
| 6 | Input Current, DACIIN 0 | 0 = Adds 0mA of input current. 1 = Adds 64mA of input current. |
| 7 | Input Current, DACIIN 1 | 0 = Adds 0mA of input current. 1 = Adds 128mA of input current. |
| 8 | Input Current, DACIIN 2 | 0 = Adds 0mA of input current. 1 = Adds 256mA of input current. |
| 9 | Input Current, DACIIN 3 | 0 = Adds 0mA of input current. 1 = Adds 512mA of input current. |
| 10 | Input Current, DACIIN 4 | 0 = Adds 0mA of input current. 1 = Adds 1024mA of input current. |
| 11 | Input Current, DACIIN 5 | 0 = Adds 0mA of input current. 1 = Adds 2048mA of input current. |
| 12 | Input Current, DACIIN 6 | 0 = Adds 0mA of input current. 1 = Adds 4096mA of input current. |
| 13 | — | Not used. |
| 14 | — | Not used. |
| 15 | — | Not used. |