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ZHCSAH3D march 2013 – september 2020 BQ51013B

PRODUCTION DATA

7.6 Typical Characteristics

Input: RX AC power		Output: RX RECT power
Efficiency: Output Power / Input Power

Figure 7-1 Rectifier Efficiency

Input: TX DC power		Output: RX RECT power
Plot: Output Power / Input Power

Figure 7-3 Light Load System Efficiency Improvement Due to Dynamic Efficiency Scaling Feature ⁽¹⁾

R_ILIM = 250 Ω and 750 Ω

Figure 7-5 Impact of Maximum Current setting (R_ILIM) on Rectifier Voltage (V_RECT)

C_OUT = 1 μf

Without Communication

Figure 7-7 Impact of Load Current on Output Ripple

Figure 7-9 1-A Instantaneous Load Dump ⁽²⁾

Figure 7-11 1-A Load Dump Full System Response

Figure 7-13 TS Fault

Figure 7-15 Adapter Insertion (V_AD = 10 V) Illustrating Break-Before-Make Operation

Figure 7-17 BQ51013B Typical Start-Up With a 1-A System Load

Figure 7-19 Adaptive Communication Limit Event Where the Current Limit is I_OUT + 50 mA (I_OUT-DC > 300 mA)

Input: TX DC power		Output: RX RECT power
Efficiency: Output Power / Input Power

Figure 7-2 System Efficiency From DC Input to DC Output

Figure 7-4 Impact of Load Current ( I_LOAD) on Rectifier Voltage (V_RECT)

Maximum Current = 1 A

Figure 7-6 Impact of Load Current on Output Voltage

Figure 7-8 V_OUT vs Temperature

Figure 7-10 1-A Load Step Full System Response

Figure 7-12 Rectifier Overvoltage Clamp (f_op = 110 kHz)

Figure 7-14 Adapter Insertion (V_AD = 10 V)

Figure 7-16 On-the-Go Enabled (V_OTG = 3.5 V) ⁽³⁾

Figure 7-18 Adaptive Communication Limit Event Where the 400 mA Current Limit is Enabled (I_OUT-DC < 300 mA)

Figure 7-20 RX Communication Packet Structure

Efficiency measured from DC input to the transmitter to DC output of the receiver. The BQ500210EVM-689 TX was used for these measurements. Measurement subject to change if an alternate TX is used.
Total droop experienced at the output is dependent on receiver coil design. The output impedance must be low enough at that particular operating frequency in order to not collapse the rectifier below 5 V.
On-the-go mode is enabled by driving EN1 high. In this test, the external PMOS is connected between the output of the BQ51013B device and the AD pin; therefore, any voltage source on the output is supplied to the AD pin.