9.3.1 Automatic/Manual Reference Clock Switching

The CDCM7005-SP supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary clock input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected by the dedicated SPI register bit (Word 0, Bit 30).

In the manual mode, the external REF_SEL signal selects one of the two input clocks:

REF_SEL [1] -> primary clock is selected

REF_SEL [0] -> secondary clock is selected

In the automatic mode, the primary clock is selected by default even if both clocks are available. In case the primary clock is not available or fails, then the input switches to the secondary clock as long until the primary clock is back. Figure 15 shows the automatic clock selection.

NOTE:

PRI_REF is the preferred clock input.

Figure 15. Behavior of STATUS_REF and PRI_SEC_CLK

In the automatic mode, the frequencies of both clock signals have to be similar, but may differ by up to 20%. The phase of the clock signal can be any.

The clock input circuitry is design to suppress glitches during switching between the primary and secondary clock in the manual and automatic mode. This avoids an undefined switching of the following circuitries.

The phase of the output clock slowly follows the new input phase. There will be no phase jump at the output. How quick the phase adjustment is done depends on the selected loop parameter, i.e., at a loop bandwidth of <100 Hz; the phase adjustment can take several ms. There is no phase build-out function supported (like in SONET/SDH applications).

Figure 16. Phase Approach of Output to New Reference Clock

9.3.2 PLL Lock for Analog and Digital Detect

The CDCM7005-SP supports two PLL lock indications: the digital lock signal or the analog lock signal. Both signals indicate logic high-level at PLL_LOCK if the PLL locks according the selected lock condition.

9.3.2.1 PLL Lock/Out-of-Lock Definition

The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and Feedback Clock (VCXO_IN clock) at the PFD (phase frequency detect) are inside a predefined lock detect window, or if no cycle-slip appears, for a pre-defined number of successive clock cycles.

The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and Feedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window or if a cycle-slip appears.

Both, the lock detect window and the number of successive clock cycles are user definable (Word 3, Bit 2-6).

Figure 17. Lock Detect Window

The lock detect window describes the maximum allowed time difference for lock detect between the rising edge of PRI_REF or SEC_REF and VCXO_IN. The time difference is detected at the phase frequency detector. The rising edge of PRI_REF or SEC_REF is taken as reference. The rising edge of VCXO_IN is outside the lock detect window if there is a phase displacement of more than +0.5 × t_(lockdetect) or –0.5 × t_(lockdetect).

9.3.2.2 Digital vs Analog Lock

Figure 18 and Figure 19 show the circuit for the digital and analog lock. The analog lock operates with an external load capacitor.

When selecting the digital PLL lock option, PLL_LOCK will possibly jitter several times between lock and out of lock until a stable lock is detected. A single low-to-high step can be reached with a wide lock detect window and high number of successive clock cycles. PLL_LOCK returns to out of lock if just one cycle is outside the lock detect window or a cycle slip occurs.

Figure 18. Digital Lock-Detect

When selecting the analog PLL Lock option, the high-pulses load the external capacitor via the internal 110-µA current source until logic high-level is reached. Therefore, more time is needed to detect logic high level, but jittering of PLL_LOCK will be suppressed in case of digital lock. The time PLL_LOCK needs to return to out of lock depends on the level of V_Out, when the current source starts to unload the external capacitor.

Figure 19. Analog Lock-Detect

9.3.3 Differential LVPECL Outputs and Single-Ended LVCMOS Outputs

The CDCM7005-SP supports up to 5 × LVPECL outputs or 10 × LVCMOS/LVTTL outputs or any combination of these. The single ended LVCMOS outputs are arranged in pairs which mean both outputs of a LVCMOS pair have the same frequency but can separately be disabled or inverted. The power up output arrangement is five LVPECL (default setting).

The LVPECL outputs are designed to terminate in to a 50-Ω load to V_CC – 2 V. The LVCMOS outputs supports the standard LVCMOS load (see Figure 13). The LVPECL and LVCMOS outputs can be enabled (normal operation) or disabled (3-state).

In addition, the output phase can be shifted by 90 degrees when using the additional div-by-4 or div-by-8 mode of the P16-Div (see Figure 20). In the default mode (after power up), the div-by-16 mode of the P16-Div is active. To change it to a 90 degree phase shift, bit 30 or bit 31 of word 1 has to be programmed accordingly. The P 16-Div has to be selected via the dedicated YxMUX to obtain the 90 degree phase shift. The outputs are switched in pairs. When selecting the 90 degree phase shift mode, the div-by-16 functions will no longer be available. The 90 degree phase shifted signal is lagging to the non-shifted signal.

Figure 20. 90 Degree Phase Shift Option of P-Divider

Figure 21 shows the LVCMOS and LVPECL output signal when 90 degree phase shift is on.

Figure 21. Output Switching Diagram

In addition, the LVCMOS supports disabled-to-low and 180° output phase shift for each output individually. When selecting the 180° phase shift together with the 90° phase shift, the respective outputs has a total phase shift of 270° (see Table 1).

If the P16-Div is selected by the FB_MUX and div-by-4 or div-by-8 is active, the 90° phase shifted clock will be synchronized to PRI_REF or SEC_REF. This means all outputs Yxx, which are switched to div-by-4 or div-by-8, are in phase to PRI_REF or SEC_REF. All other outputs are 90° phase shifted with leading phase.

9.3.4 Frequency Hold-Over Mode

The HOLD function is a useful feature which helps the designer to improve the system reliability. The HOLD function holds the output frequency in case the input reference clock fails or becomes disrupted. During HOLD, the charge pump switches off (3-state) freezing the last valid output frequency. The hold function will release after a valid reference clock comes back. For proper HOLD function, the analog PLL lock detect mode has to be active.

The following register settings are involved with the HOLD function:

• Lock Detect Window (Word 3, Bit 2, 3, 6): Defines the window in ns inside the lock is valid. The size is
  3.5 ns, 8.5 ns, 18.5 ns, or a certain frequency offset. Lock sets if reference clock and the feedback clock are inside this predefined lock-detect window for a pre-selected number of successive cycles or if no frequency offset appears.
• Out-of-Lock: Defines the out-of-lock condition: If the reference clock and the feedback clock at the PFD are outside the predefined Lock Detect Window or if a certain frequency offset occurs.
• Cycle-Slip (Word 3, Bit 6): A Frequency offset occurs if a certain frequency offset between reference frequency and feedback frequency (VCXO) at PFD input is detected. The minimum detectable frequency offset depends on the device setting and can be calculated:

• Number of Clock Cycles (Word 3, Bit 4, 5): Defines the number of successive PFD cycles which have to occur inside the lock window to set Lock detect. This applies not for out-of-lock condition.
• Hold-Function (Word 3, Bit 9): Selects HOLD function (see more details below).
• Hold-Trigger (Word 3, Bit 11): Defines whether the HOLD function is always activated (Bit 11 = [1]) or whether it is dependent on the state of the analog PLL lock detect output (Bit 11 = [0]). In the latter case, HOLD is activated, if lock is set (high) and de-activated if Lock is reset (low).
• Analog PLL Lock Detect (Word 1, Bit 29): Analog lock output charges or discharges an external capacitor with every valid lock cycle. The time constant for Lock detect can be set by the value of the capacitor.

The CDCM7005 supports two types of HOLD functions, one external controllable HOLD mode and one internal mode, HOLD.

With the external HOLD function the charge pump can directly be switched into 3-state (pin H8 [BGA] or pin 14 [QFN] can be programmed for HOLD [Word 2, Bit 29]). This function is also available via SPI register (Word 2, Bit 31).

If logic low is applied to the HOLD pin, the charge pump will be switched to 3-state. After the HOLD pin is released, the charge pump is switched back in to normal operation with the next valid reference clock cycle at PRI_REF or SEC_REF and the next valid feedback clock cycle at the PFD. During HOLD, the P divider and all outputs Yx are at normal operation.

HOLD-Over-Function: The PLL has to be in lock to start the HOLD function. It switches the charge pump in to 3-State when an out-of-lock event occurs. It leaves the 3-state charge pump state when the reference clock is back. Then it starts a locking sequence of 64 cycles before it goes back to the beginning of the HOLD-over loop. The dedicated looking sequence and a digital phase alignment enable a fast lock.

Figure 22. Frequency HOLD-Over Function

9.3.5 Charge Pump Preset to VCC_CP / 2

The preset charge pump to VCC_CP/2 is a useful feature to quickly set the center frequency of the VC(X)O after powerup or reset. The adequate control voltage for the VC(X)O will be provided to the charge-pump output by an internal voltage divider of 1 kΩ/1 kΩ to VCC_CP and GND (VCC_CP/2).

This feature helps to get the initial frequency accuracy, i.e. required at common public radio interface (CPRI) or open base station architecture initiative (OBSAI).

The preset charge pump to VCC_CP/2 can be set and reset by SPI register (word 2, bit 3). This feature must be disabled for PLL locking.

9.3.6 Charge Pump Current Direction

The direction of the charge pump (CP) current pulse can be changed by the SPI register (word 2, bit 2). It determines in which direction the CP current regulates (reference clock leads to feedback clock). Most applications use the positive CP output current (power-up condition) because of the use of a passive loop filter. The negative CP current is useful when using an active loop filter concept with inverting operational amplifier. Figure 23 shows the internal PFD signal and the corresponding CP current.

NOTE:

The purpose of the PFD pluse width delay is to improve spurious suppression.

Figure 23. Charge Pump Current Direction (VCXO and VCO Support)

9.5.1 SPI Control Interface

The serial interface of the CDCM7005-SP is a simple SPI-compatible interface for writing to the registers of the device and consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. There are four 32 bit wide registers, which can be addressed by the two LSBs of a transferred word (bit 0 and bit 1). Every transmitted word must have 32 bits, starting with MSB first. Each word can be written separately. Bit 7, 8, 10, and Bit 12 to 31 of Word 3 are reserved for factory test purposes and must be filled with zeros. The transfer is initiated with the falling edge of CTRL_LE; as long as CTRL_LE is high, no data can be transferred. During CTRL_LE, low data can be written. The data has to be applied at CTRL_DATA and has to be stable before the rising edge of CTRL_CLK. The transmission is finished by a rising edge of CTRL_LE. With the rising edge of CTRL_LE, the new word is asynchronously transferred to the internal register (for example, N, M, P, ...). Each word has to be separately transmitted by this procedure. Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCC.

Figure 24. Timing Diagram SPI Control Interface

The SPI serial protocol accepts word Write operation only. There is neither a read, acknowledge, nor a handshake operation.

The following four words include the register settings of the programmable functions of the CDCM7005-SP. It can be modified to the customer application by changing one or more bits. It comes up with a default register setting after power up or if the power down (PD) control signal is applied. The default setting is shown in column five of the following words.

It is recommended to program Word 0, Word 1, Word 2 and Word 3 right after power up and PD becomes HIGH.

A low active function is shown as [0] and a high active function is shown as [1].

9.5.2 Functional Description of the Logic