ZHCSJU7 May 2019 DRV8340-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1
Three Phase Smart Gate Drivers
- 8.3.1.1
PWM Control Modes
- 8.3.1.1.1 6x PWM Mode (PWM_MODE = 000b or MODE Pin Tied to AGND)
- 8.3.1.1.2 3x PWM Mode (PWM_MODE = 001b or MODE Pin = 18 kΩ to AGND)
- 8.3.1.1.3 1x PWM Mode (PWM_MODE = 010b or MODE Pin = 75 kΩ to AGND)
- 8.3.1.1.4 Independent Half-Bridge PWM Mode (PWM_MODE = 011b or MODE Pin is > 1.5 MΩ to AGND or Hi-Z)
- 8.3.1.1.5 Phases A and B are Independent Half-Bridges, Phase C is Independent FET (MODE = 100b)
- 8.3.1.1.6 Phases B and C are Independent Half-Bridges, Phase A is Independent FET (MODE = 101b or MODE Pin is 75 kΩ to DVDD)
- 8.3.1.1.7 Phases A is Independent Half-Bridge, Phases B and C are Independent FET (MODE = 110b or MODE Pin is 18 kΩ to DVDD)
- 8.3.1.1.8 Independent MOSFET Drive Mode (PWM_MODE = 111b or MODE Pin = 0.47 kΩ to DVDD)
- 8.3.1.2 Device Interface Modes
- 8.3.1.3 Gate Driver Voltage Supplies
- 8.3.1.4 Smart Gate Drive Architecture
- 8.3.1.1
PWM Control Modes
- 8.3.2 DVDD Linear Voltage Regulator
- 8.3.3 Pin Diagrams
- 8.3.4
Gate Driver Protective Circuits
- 8.3.4.1 VM Supply Undervoltage Lockout (UVLO)
- 8.3.4.2 VCP Charge Pump Undervoltage Lockout (CPUV)
- 8.3.4.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 8.3.4.4 Gate Driver Fault (GDF)
- 8.3.4.5 Thermal Warning (OTW)
- 8.3.4.6 Thermal Shutdown (OTSD)
- 8.3.4.7 Open Load Detection (OLD)
- 8.3.4.8 Offline Shorts Diagnostics
- 8.3.4.9 Reverse Supply Protection
- 8.3.1
Three Phase Smart Gate Drivers
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 Status Registers
- 8.6.2
Control Registers
- 8.6.2.1 IC1 Control Register (Address = 0x04) [reset = 0x00]
- 8.6.2.2 IC2 Control Register (address = 0x05) [reset = 0x40]
- 8.6.2.3 IC3 Control Register (Address = 0x06) [reset = 0xFF]
- 8.6.2.4 IC4 Control Register (Address = 0x07) [reset = 0xFF]
- 8.6.2.5 IC5 Control Register (Address = 0x08) [reset = 0xFF]
- 8.6.2.6 IC6 Control Register (Address = 0x09) [reset = 0x99]
- 8.6.2.7 IC7 Control Register (Address = 0x0A) [reset = 0x99]
- 8.6.2.8 IC8 Control Register (Address = 0x0B) [reset = 0x99]
- 8.6.2.9 IC9 Control Register (Address = 0x0C) [reset = 0x2F]
- 8.6.2.10 IC10 Control Register (Address = 0x0D) [reset = 0x61]
- 8.6.2.11 IC11 Control Register (Address = 0x0E) [reset = 0x00]
- 8.6.2.12 IC12 Control Register (Address = 0x0F) [reset = 0x2A]
- 8.6.2.13 IC13 Control Register (Address = 0x10) [reset = 0x7F]
- 8.6.2.14 IC14 Control Register (Address = 0x10) [reset = 0x00]
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PHP|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PHP|48
訂購(gòu)信息
3 說明
DRV8340-Q1 器件是一款適用于三相應(yīng)用的 集成式柵極驅(qū)動(dòng)器。此器件具有三個(gè)半橋柵極驅(qū)動(dòng)器，每個(gè)驅(qū)動(dòng)器都能夠驅(qū)動(dòng)高側(cè)和低側(cè) N 溝道功率 MOSFET。專用源極與漏極引腳支持對(duì)電磁閥應(yīng)用進(jìn)行獨(dú)立 MOSFET 控制。DRV8340-Q1 使用集成式電荷泵為高側(cè) MOSFET 生成足夠的柵極驅(qū)動(dòng)電壓，并使用線性穩(wěn)壓器為低側(cè) MOSFET 生成足夠的柵極驅(qū)動(dòng)電壓。此智能柵極驅(qū)動(dòng)架構(gòu)支持高達(dá) 1A 的峰值柵極驅(qū)動(dòng)拉電流和 2A 的峰值柵極驅(qū)動(dòng)灌電流。DRV8340-Q1 可由單一電源供電，支持適用于柵極驅(qū)動(dòng)器的 5.5 至 60V 寬輸入電源電壓范圍。
6x、3x、1x 和獨(dú)立輸入 PWM 模式可簡(jiǎn)化與控制器電路的連接。柵極驅(qū)動(dòng)器和器件的配置設(shè)置具有高度可配置性，可通過 SPI 或硬件 (H/W) 接口實(shí)現(xiàn)。
提供了低功耗睡眠模式，實(shí)現(xiàn)較低的靜態(tài)電流消耗。針對(duì)欠壓鎖定、電荷泵故障、MOSFET 過流、MOSFET 短路、相位節(jié)點(diǎn)電源和接地短路、柵極驅(qū)動(dòng)器故障和過熱情況提供內(nèi)部保護(hù)功能。故障狀況及故障詳情可通過 SPI 器件型號(hào)的器件寄存器顯示在 nFAULT 引腳上。
器件信息(1)
| 器件型號(hào) | 封裝 | 封裝尺寸（標(biāo)稱值） |
|---|---|---|
| DRV8340-Q1 | HTQFP (48) | 7.00mm × 7.00mm |
- 如需了解所有可用封裝，請(qǐng)參閱數(shù)據(jù)表末尾的可訂購(gòu)產(chǎn)品附錄。
簡(jiǎn)化原理圖
