ZHCSG08E October 2016 – January 2021 DRV8702-Q1 , DRV8703-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Bridge Control
- 7.3.2 MODE Pin
- 7.3.3 nFAULT Pin
- 7.3.4 Current Regulation
- 7.3.5 Amplifier Output (SO)
- 7.3.6 PWM Motor Gate Drivers
- 7.3.7 IDRIVE Pin (DRV8702-Q1 Only)
- 7.3.8 Dead Time
- 7.3.9 Propagation Delay
- 7.3.10 Overcurrent VDS Monitor
- 7.3.11 VDS Pin (DRV8702-Q1 Only)
- 7.3.12 Charge Pump
- 7.3.13 Gate Drive Clamp
- 7.3.14
Protection Circuits
- 7.3.14.1 VM Undervoltage Lockout (UVLO2)
- 7.3.14.2 Logic Undervoltage (UVLO1)
- 7.3.14.3 VCP Undervoltage Lockout (CPUV)
- 7.3.14.4 Overcurrent Protection (OCP)
- 7.3.14.5 Gate Driver Fault (GDF)
- 7.3.14.6 Thermal Shutdown (TSD)
- 7.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)
- 7.3.14.8 Reverse Supply Protection
- 7.3.15 Hardware Interface
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.13 Gate Drive Clamp
A clamping structure limits the gate-drive output voltage to the VC(GS) voltage to protect the power FETs from damage. The positive voltage clamp is realized using a series of diodes. The negative voltage clamp uses the body diodes of the internal predriver FET.
Figure 7-16 Gate Drive Clamp