7.3.1 High Voltage Start-up Regulator

The LM5141 contains an internal high voltage VCC bias regulator that provides the bias supply for the PWM controller and the gate drivers for the external MOSFETs. The input pin (VIN) can be connected directly to an input voltage source up to 65 V. The output of the VCC regulator is set to 5 V. When the input voltage is below the VCC set-point level, the VCC output will track VIN with a small voltage drop. In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute maximum voltage rating of 70 V including line or load transients. Voltage ringing on the VIN pin that exceeds the Absolute Maximum Ratings can damage the IC. Use a high quality bypass capacitor between VIN and ground to minimize ringing.

7.3.2 VCC Regulator

The VCC regulator output current limit is 75 mA (minimum). At power-up, the regulator sources current into the capacitors connected to the VCC pin. When the voltage on the VCC pin exceeds 3.4 V the output is enabled and the soft-start sequence begins. The output remains active unless the voltage on the VCC pin falls below the VCC_(UVLO) threshold of 3.2 V (typical) or the enable pin is switched to a low state. The recommended range for the VCC capacitor is 2.2 µF to 4.7 µF

An internal 5-V linear regulator generates the VDDA bias supply. Bypass VDDA with a 100-nF or greater ceramic capacitor to ensure a low noise internal bias rail. Normally VDDA is 5 V, but there are two operating conditions where it regulates at 3.3 V. The first is in skip cycle mode with VOUT of 3.3 V. The second is when V_IN is less than 5 V. Under these conditions both VCC and VDD will drop below 5 V. Internal power dissipation in the VCC Regulator can be minimized by connecting the VCCX pin to a 5 V output or to an external 5 V supply. If VCCX > 4.5 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. If VCCX is unused, it should be grounded. Never connect the VCCX pin to a voltage greater than 6.5 V.

7.3.3 Oscillator

The LM5141 has an internal trimmed oscillator with two frequency options: 2.2 MHz, or 440 kHz. With the OSC pin connected to VDDA the oscillator frequency is 2.2 MHz. With the OSC pin grounded, the oscillator frequency is 440 kHz. The state of the OSC pin is read and latched during VCC power-up and cannot be changed until VCC drops below the VCC_(UVLO) threshold.

The oscillator frequency can be modulated up or down from the nominal oscillator frequency (2.2 MHz or 440 kHz) on demand by connecting a resistor from the RT pin to ground (refer to Figure 19). To disable the frequency modulation option, the RT pin can be grounded or left open. If the RT pin is connected to ground during power-up the frequency modulation option is latch-off and cannot be changed unless VCC is allowed to drop below the VCC_(UVLO) threshold. If the RT pin is left open during power-up the frequency modulation option will be disabled, but it can be enabled at a later time by switching in a valid RT resistor. When the frequency modulation option is disabled, the LM5141 will operate at the internal oscillator frequency (2.2 MHz or 440 kHz).

On power up, after soft-start is complete and the output voltage is in regulation, a 16 µs timer is initiated. If a valid RT resistor is connected, the LM5141 will switch to the frequency set by the RT resistor n the completion of the 16 µs time delay.

The modulation range for 2.2 MHz is 1.8 MHz to 2.53 MHz (refer to Table 1). If an RT resistor value > 95 kΩ (typical) is placed on the RT pin, the LM5141 controller will assume that the RT pin is open, and will use the internal oscillator. If an RT resistor < 27 kΩ (typical) is connected, the controller will use the internal oscillator. To calculate an RT resistor for a specific oscillator frequency, use Equation 1 for the 2.2 MHz frequency range or Equation 2 for the 440 kHz frequency range.

Equation 1.

where

• RT is kΩ and Fsw is in MHz

Equation 2.

where

• RT is in kΩ and Fsw is in kHz

Figure 19. RT Connection Circuit, 2.2 MHz

Figure 20. RT Connection Circuit, 440 kHz

An alternative method to modulate the oscillator frequency is to use an analog voltage connected to the RT pin through a resistor. See Figure 21. An analog voltage of 0.0 V to 0.6 V will modulate the oscillator frequency between 1.8 MHz to 2.53 MHz (OSC at 2.2 MHz), or 300 kHz to 500 kHz (OSC at 440 kHz). The analog voltage source must be able to sink current.

Figure 21. Analog Voltage Control of the Oscillator Frequency

When the LM5141 is in the low I_Q standby mode, the controller will set the RT pin to a high impedance state and ignore the RT resistor. After coming out of standby mode, the controller will monitor the RT pin. If a valid resistor is connected, and there have been 16 µs of continuous switching without a zero-crossing event, the LM5141 will switch to the frequency set by the RT resistor.

7.3.4 Synchronization

To synchronize the LM5141 to an external source, apply a logic level clock signal to the DEMB pin. The synchronization range is 350 kHz to 550 kHz when the internal oscillator is set to 440 kHz. When the internal oscillator is set to 2.2 MHz, the synchronization range is 1.8 MHz to 2.6 MHz. If there is a valid RT resistor and a synchronization signal, the LM5141 with ignore the RT resistor and synchronize the controller to the external clock. Under low V_IN conditions, when the minimum toff time is reached (100ns), the synchronization clock will be ignored to allow the frequency to drop to maintain output voltage regulation.

7.3.5 Frequency Dithering (Spread Spectrum)

The LM5141 provides a frequency dithering option that is enabled by connecting a capacitor from the DITH pin to AGND. A triangular waveform centered at 1.2 V is generated across the C_DITH capacitor. Refer to Figure 22. The triangular waveform modulates the oscillator frequency by ±5% of the nominal frequency set by the OSC pin or by an RT resistor. The C_DITH capacitance value sets the rate of the low frequency modulation. A lower C_DITH capacitance will modulate the oscillator frequency at a faster rate than a higher capacitance. For the dithering circuit to effectively reduce the peak EMI, the modulation rate must be less than the oscillator frequency (Fsw). Equation 3 calculates the DITH pin capacitance required to set the modulation frequency, FMOD.

Equation 3.

If the DITH pin is connected to VDDA during power-up the Dither feature is latch-off and cannot be changed unless VCC is allowed to drop below the VCC_(UVLO) threshold. If the DITH pin is connected to ground on power up, Dither will be disabled, but it can be enabled by raising the DITH pin voltage above ground and connecting it to C_DITH. When the LM5141 is synchronized to an external clock, Dither is disabled.

Figure 22. Dither Operation

7.3.6 Enable

The LM5141 has an enable input EN for start-up and shutdown control of the output. The EN pin can be connected to a voltage as high as 70 V. If the enable input is greater than 2.0 V the output is enabled. If the enable pin is pulled below 0.8 V, the output will be in shutdown, and the LM5141 is switched to a low I_Q shutdown mode, with a 10-µA typical current drawn from the VIN pin. It is not recommended to leave the EN pin left floating.

7.3.7 Power Good

The LM5141 includes an output voltage monitoring function to simplify sequencing and supervision. The power good function can be used to enable circuits that are supplied by the output voltage rail or to turn-on sequenced supplies. The PG pin switches to a high impedance state when the output voltage is in regulation. The PG signal switches low when the output voltage drops below the lower power good threshold (92% typical) or rises above the upper power good threshold (110% typical). A 25 μs deglitch filter prevents any false tripping of the power good signal due to transients. A pull-up resistor of 10 kΩ is recommended from the PG pin to the relevant logic rail. Power good is asserted low during soft-start and when the buck converter is disabled by EN.

7.3.8 Output Voltage

The LM5141 output can be configured for one of the two fixed output voltages with no external feedback resistors, or the output can be adjusted to the desired voltage using an external resistor divider. V_OUT can be configured as a 3.3-V output by connecting the FB pin to VDDA, or a 5-V output by connecting the FB pin to ground with a maximum resistance of 500 Ω. The FB connections (either VDDA or GND) are detected during power up.

The configuration setting is latched and cannot be changed until the LM5141 is powered down with VCC falling below VCC_(UVLO) (3.4 V typical) and then powered up again.

Alternatively the output voltage can be set using an external resistive dividers from the output to the FB pin. The output voltage adjustment range is between 1.5 V and 15 V. The regulation threshold at the FB pin is 1.2 V (V_REF). To calculate R_FB1 and R_FB2 use Equation 4. Refer to Figure 23:

Equation 4.

The recommend starting point is to select R_FB1 between 10 kΩ to 20 kΩ.

The Thevenin equivalent impedance of the resistive divider connected to the FB pin must be greater than 5 kΩ for the LM5141 to detect the divider and set the controller to the adjustable output mode. Refer to Equation 5.

Equation 5.

If a low I_Q mode is required, take care when selecting the external resistors. The extra current drawn from the external divider is added to the LM5141 I_STANDBY current (35 μA typical). The divider current reflected to VIN is divided down by the ratio of V_OUT/V_IN. For example, if V_IN is 12V and V_OUT is set to 5.5 V with R_FB1 10 kΩ, and R_FB2 = 35.7 kΩ, the input current at VIN required to supply the current in the feedback resistors is:

Equation 6.

where

• V_IN = 12 V

The total input current in this condition will be:

Equation 7.

Figure 23. Voltage Feedback

7.3.8.1 Minimum Output Voltage Adjustment

There are two limitations to the minimum output voltage adjustment range: the LM5141 voltage reference of 1.2 V and the minimum switch node pulse width, t_SW.

The minimum controllable on-time at the switch node (t_SW) limits the voltage conversion ratio (V_OUT/V_IN). For fixed-frequency PWM operation, the voltage conversion ratio should meet the following condition:

Equation 8.

Where t_SW is 70 ns (typical) and Fsw is the switching frequency. If the desired voltage conversion ratio does not meet the above condition, the controller transitions from fixed frequency operation into a pulse skipping mode to maintain regulation of the output voltage.

For example if the desired output voltage is 3.3 V with a V_IN of 20 V and operating at 2.2 MHz, the voltage conversion ratio test is satisfied:

Equation 9.

0.165> 0.154

For wide V_IN applications and lower output voltages, an alternative is to use the LM5141 with a 440-kHz oscillator frequency. Operating at 440 kHz, the limitation of the minimum t_SW time is less significant. For example, if a 1.8-V output is required with a V_IN of 50 V:

Equation 10.

0.036> 0.0308

7.3.9 Current Sense

There are two methods to sense the inductor current of the buck converter. The first is using current sense resistor in series with the inductor and the second is to use the dc resistance of the inductor (DCR sensing). Figure 24 illustrates inductor current sensing using a current sense resistor. This configuration continuously monitors the inductor current providing accurate current-limit protection. For the best current-sense accuracy and over current protection, use a low inductance ±1% tolerance current-sense resistor between the inductor and output, with a Kelvin connection to the LM5141 sense amplifier.

If the peak differential current signal sensed from CS to VOUT exceeds 75 mV, the current limit comparator immediately terminates the HO output for cycle-by-cycle current limiting.

Equation 11.

where

• V_(CS) = 75 mV

I_OUT(MAX) is the over current set point which is set higher than the maximum load current to avoid tripping the over current comparator during load transients. ΔI is the peak-peak inductor ripple current.

Figure 24. Current Sense

7.3.10 DCR Current Sensing

For high-power applications which do not require high accuracy current-limit protection, DCR sensing may be preferable. This technique provides lossless and continuous monitoring of the output current using an RC sense network in parallel with the inductor. Using an inductor with a low DCR tolerance, the user can achieve a typical current limit accuracy within the range of ±10% to ±15% at room temperature.

Components R_CS and C_CS in Figure 25 create a low-pass filter across the inductor to enable differential sensing of the voltage drop across inductor DCR. When R_CS × C_CS is equal to L_OUT/R_DCR, the voltage developed across the sense capacitor, C_CS, is a replica of the inductor DCR voltage waveform. Choose the capacitance of C_CS to be greater than 0.1 μF to maintain a low impedance sensing network, thus reducing the susceptibility of noise pickup from the switch node. Carefully observe the PCB layout guidelines to ensure the noise and DC errors do not corrupt the differential current-sense signals applied across the CS and VOUT pins.

The voltage drop across C_CS:

Equation 12.

Figure 25. DCR Current Sensing

R_CSC_CS = L_OUT/R_DCR → accurate DC and AC current sensing

If the RC time constant is not equal to the L_OUT/L_DRC time constant there will be an error

R_CSC_CS > L_OUT/R_DCR → DC level still correct, the AC amplitude will be attenuated

R_CSC_CS < L_OUT/R_DCR→ DC level still correct, the AC amplitude will be amplified

7.3.11 Error Amplifier and PWM Comparator

The LM5141 has a high-gain transconductance amplifier which generates an error current proportional to the difference between the feedback voltage and an internal precision reference (1.2 V). The output of the transconductance amplifier is connected to the COMP pin allowing the user to provide external control loop compensation. Generally for current mode control a type II network is recommended.

7.3.12 Slope Compensation

The LM5141 provides internal slope compensation to ensure stable operation with a duty cycle greater than 50%. To correctly use the internal slope compensation, the inductor value must be calculated based on the following guidelines (Equation 12 assumes an inductor ripple current of 30%):

Equation 13.

• Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost and improves transient response at the cost of reduced efficiency due to higher peak currents.
• Higher inductance values decrease the peak-to-peak inductor current typically increases efficiency by reducing the RMS current at the cost of requiring larger output capacitors to meet load-transient specifications.

7.3.13 Hiccup Mode Current Limiting

The LM5141 includes an optional hiccup mode protection function that is enabled when a capacitor is connected to the RES pin. In normal operation the RES capacitor is discharged to ground. If 512 consecutive cycles of cycle-by-cycle current limiting occur, the SS pin capacitor is pulled low and the HO and LO outputs are disabled (refer to Figure 26). A 20-μA current source begins to charge the RES capacitor.

When the RES pin charges to 1.2 V, the RES pin is pulled low and the SS capacitor begins to charge. The 512 cycle hiccup counter is reset if 4 consecutive switching cycles occur without exceeding the current limit threshold. The controller is in forced PWM (FPWM) continuous conduction mode when the DEMB pin is connected to VDDA. In this mode the SS pin is clamped to a level 200 mV above the feedback voltage to the internal error amplifier. This ensures that SS can be pulled low quickly during a brief overcurrent event and prevent overshoot of VOUT when the overcurrent condition is removed.

If DEMB=0 V, the controller operates in diode emulation with light loads (discontinuous conduction mode) and the SS pin is allowed to charge to VDDA. This reduces the quiescent current of the LM5141. If 32 or more cycle-by-cycle current limit events occur, the SS pin is clamped to 200 mV above the feedback voltage to the internal error amplifier until the hiccup counter is reset. Thus, if a momentary overload occurs that causes at least 32 cycles of current limiting, the SS capacitor voltage will be slightly higher than the FB voltage and will control VOUT during overload recovery.

Figure 26. Hiccup Mode

7.3.14 Standby Mode

The LM5141 operates with peak current mode control such that the compensation voltage is proportional to the peak inductor current. During no-load or light load conditions, the output capacitor will discharge very slowly. As a result the compensation voltage will not demand a driver output pulses on a cycle-by-cycle basis. When the LM5141 controller detects that there have been 16 missing switching cycles, it enters Standby Mode and switches to a low IQ state to reduce the current drawn from VIN. For the LM5141 to go into a Standby Mode, the controller must be programmed for diode emulation (DEMB pin < 0.4 V). The typical IQ in Standby Mode is 35 μA with VOUT regulating at 3.3 V.

7.3.15 Soft-Start

The soft-start feature allows the controller to gradually reach the steady state operating point, thus reducing Start-up stresses and surges. The LM5141 regulates the FB pin to the SS pin voltage or the internal 1.2-V reference, whichever is lower. At the beginning of the soft-start sequence when SS = 0 V, the internal 20 µA soft-start current source gradually increases the voltage on an external soft-start capacitor connected to the SS pin, resulting in a gradual rise of the FB and output voltages. The controller is in the forced PWM (FPWM) mode when the DEMB pin is connected to VDDA. In this mode, the SS pin is clamped at 200 mV above the feedback voltage. This ensures that SS will be pulled low quickly when FB falls during brief over-current events to prevent overshoot of VOUT during recovery. SS can be pulled low with an external circuit to stop switching, but this is not recommended. Pulling SS low will result in COMP being pulled down internally as well. If the controller is operating in FPWM mode (DEMB = VDDA), LO will remain on and the low-side MOSFET will discharge the VOUT capacitor resulting in large negative inductor current. In contrast when the LM5141 pulls SS low internally due to a fault condition, the LO gate driver is disabled.

7.3.16 Diode Emulation

A fully synchronous buck controller implemented with a free-wheel MOSFET rather than a diode has the capability to sink negative current from the output in certain conditions such as light load, over-voltage, and pre-bias start-up. The LM5141 provides a diode emulation feature that can be enabled to prevent reverse (drain to source) current flow in the low-side free-wheel MOSFET. The diode emulation feature is configured with the DEMB pin. To enable diode emulation, connect the DEMB pin to ground. When configured for diode emulation, the low-side MOSFET is disabled when reverse current flow is detected. The benefit of this configuration is lower power loss at no load or light load conditions and the ability to turn on into a pre-biased output without discharging the output. The negative effect of diode emulation is degraded light load transient response times. Enabling the diode emulation feature is recommended to allow discontinuous conduction operation. If continuous conduction operation is desired, the DEMB pin should be tied to VDDA.

7.3.17 High and Low Side Drivers

The LM5141 contains N-channel MOSFET gate drivers and an associated high-side level shifter to drive the external N-channel MOSFETs. The high-side gate driver works in conjunction with an external bootstrap diode D_BST, and bootstrap capacitor C_BST (refer to Figure 27). During the on-time of the low-side MOSFET, the SW pin voltage is approximately 0 V and C_BST is charged from VCC through the D_BST. A 0.1-μF or larger ceramic capacitor, connected with short traces between the HB and SW pin is recommended.

The LO and HO outputs are controlled with an adaptive dead-time methodology which ensures that both outputs (HO and LO) are never enabled at the same time, preventing cross conduction. When the controller commands LO to be enabled, the adaptive dead-time logic first disables HO and waits for the HO-SW voltage to drop below 2.5 V typical. LO is then enabled after a small delay (HO falling to LO rising delay). Similarly, the HO turn-on is delayed until the LO voltage has dropped below 2.5 V. HO is then enabled after a small delay (LO falling to HO rising delay). This technique ensures adequate dead-time for any size N-channel MOSFET device or parallel MOSFET configurations. Caution is advised when adding series gate resistors, as this may decrease the effective dead-time. Each of the high and low-side drivers have independent driver source and sink output pins. This allows the user to adjust drive strength to optimize the switching losses for maximum efficiency and to control the slew rate for reduced EMI. The selected N-channel high-side MOSFET determines the appropriate boost capacitance values C_BST in the Figure 27 according to Equation 13.

Equation 14.

Where Q_G is the total gate charge of the high-side MOSFET and ΔV_BST is the voltage variation allowed on the high-side MOSFET driver after turn-on. Choose ΔV_BST such that the available gate-drive voltage is not significantly degraded when determining C_BST. A typical range of ΔV_BST is 100 mV to 300 mV. The bootstrap capacitor should be a low-ESR ceramic capacitor. A minimum value of 0.1 μF to 0.47 μF is best in most cases. The gate threshold of the high-side and low-side MOSFETs should be a logic level variety approporiate for 5-V gate drive.

Figure 27. Drivers