ZHCSIM2D June 2010 – August 2021 PCM9211
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSV | RSV | RSV | PSCKAUTO | RSV | PSCK2 | PSCK1 | PSCK0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| PSCKAUTO: PLL SCK Dividing Ratio Automatic Control Setting | |||
| 0: | Disable (default) | ||
| 1: | Enable | ||
| This register is used to set the PLL SCK dividing ratio automatic control function. SCK setting is automatically set depending on the input sampling frequency. | |||
| 512fS: 54 kHz and below | |||
| 256fS: 54 kHz to 108 kHz | |||
| 128fS: 108 kHz and above or unlocked | |||
| The register setting of PSCKAUTO is prioritized higher than the PSCK[2:0] register setting. For instance, if PSCKAUTO = 1, the PSCK[2:0] register setting is ignored. To use this function, the XTI clock source is required. | |||
| PSCK[2:0]: DIR Recovered Clock Frequency Setting | |||
| 000: | 128fS | ||
| 001: | Reserved | ||
| 010: | 256fS (default) | ||
| 011: | Reserved | ||
| 100: | 512fS | ||
| 101: | Reserved | ||
| 110: | Reserved | ||
| 111: | Reserved | ||