9.3.1 Power Supply

To facilitate system design, the TAS5721 needs only a 3.3-V supply in addition to the PVDD power-stage supply. The required sequencing of the power supplies is shown in the Recommended Use Model section. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BSTRPx) and power-stage supply pins (PVDD). The gate drive voltage (GVDD_REG) is derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BSTRPx) to the power-stage output pin (SPK_OUTx). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. As shown in the Typical Application section, it is recommended to use ceramic capacitors, for the bootstrap supply pins. These capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD pin is decoupled with a ceramic capacitor placed as close as possible to each supply pin, as shown in the Typical Application section.

The TAS5721 is fully protected against erroneous power-stage turn-on due to parasitic gate charging.

9.3.2 I²C Address Selection and Fault Output

ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the Typical Application section in order to set the I²C address. Pulling this pin HIGH through the resistor results in setting the I²C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in setting the address to 0011010 (0x34).

During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to it's default state when register 0x02 is cleared. The device will pull the fault pin low for over-current, over-temperature, over-voltage lock-out, and under-voltage lock-out.

9.3.3 Device Protection System

9.3.4 Clock, Auto Detection, and PLL

The TAS5721 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the Clock Control Register section.

The TAS5721 checks to verify that SCLK is a specific value of 32 f_S, 48 f_S, or 64 f_S. The DAP only supports a 1 × f_S LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock rates as defined in the clock control register.

TAS5721 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute) and then force PLL to operate in a reduced capacity using the internal oscillator as a reference clock. Once the clocks are stable, the system will auto detect the new rate and revert to normal operation. During this process, the default volume will be restored in a single step (also called hard unmute) by default. If desired, the unmuting process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0x0E).

9.3.5 PWM Section

The TAS5721 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP and outputs up to three PWM audio output channels.

The PWM modulation block has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. It is important to note that for any applications with PVDD greater than 18 V, the maximum modulation index must be set to 93.8%.

9.3.6 SSTIMER Functionality

The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is shut down, the drivers are placed in the high-impedance state and transition slowly down through a 3-kΩ resistor, similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin capacitance. The SSTIMER capacitor size determines the start-up time, 2200 pF is the maximum recommended value. The SSTIMER pin can be left floating when using BD modulation, but leaving the capacitor connected does not represent any issue.

9.3.7 2.1-Mode Support

The TAS5721 uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode operation. To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit D2 must be set to 1. The SSTIMER pin should be left floating in this mode.

9.3.8 PBTL-Mode Support

The TAS5721 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected after the LC filter. In order to put the part in PBTL configuration, the PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should be written with a value of 0x01 10 32 45. Also, the PWM shutdown register (0x19) should be written with a value of 0x3A.

9.3.9 I²C Serial Control Interface

9.3.9.2 Single-Byte Write

As shown in Figure 50, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I²C device address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5721 internal memory address being accessed. After receiving the address byte, the TAS5721 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5721 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer.

Figure 50. Single-Byte Write Transfer

9.3.9.3 Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the DAP as shown in Figure 51. After receiving each data byte, the TAS5721 responds with an acknowledge bit.

Figure 51. Multiple-Byte Write Transfer

9.3.9.4 Single-Byte Read

As shown in Figure 52, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5721 address and the read/write bit, TAS5721 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5721 address and the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5721 again responds with an acknowledge bit. Next, the TAS5721 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.

Figure 52. Single-Byte Read Transfer

9.3.9.5 Multiple-Byte Read

A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TAS5721 to the master device as shown in Figure 53. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 53. Multiple Byte Read Transfer

9.3.10 Dynamic Range Control (DRC)

The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/right channels and one DRC for the subchannel.

The DRC input/output diagram is shown in Figure 54.

Refer to GDE software tool for more description on T, K, and O parameters.

Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
 • Each DRC has adjustable threshold, offset, and compression levels.
 • Programmable energy, attack, and decay time constants
 • Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
    and decay times can be set slow enough to avoid pumping.

Figure 54. Dynamic Range Control

T = 9.23 format, all other DRC coefficients are 3.23 format

Figure 55. DRC Structure

9.3.11 Bank Switching

The TAS5721 uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in three banks. The user can program which sample rates map to each bank. By default, bank 1 is used in 32-kHz mode, bank 2 is used in 44.1- or 48-kHz mode, and bank 3 is used for all other rates. Combined with the clock-rate autodetection feature, bank switching allows the TAS5721 to detect automatically a change in the input sample rate and switch to the appropriate bank without any MCU intervention.

An external controller configures bankable locations (0x29-0x36, 0x3A-0x3F, and 0x58-0x5F) for all three banks during the initialization sequence.

If auto bank switching is enabled (register 0x50, bits 2:0) , then the TAS5721 automatically swaps the coefficients for subsequent sample rate changes, avoiding the need for any external controller intervention for a sample rate change.

By default, bits 2:0 have the value 000; indicating that bank switching is disabled. In that state, updates to bankable locations take immediate effect. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any subsequent write to bankable locations updates the coefficient banks stored outside the DAP. After updating all the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes the system state to automatic bank switching mode. In automatic bank switching mode, the TAS5721 automatically swaps banks based on the sample rate.

9.3.12 Serial Data Interface

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5721 DAP accepts serial data in 16-, 20-, or 24-bit left-justified, right-justified, and I²S serial data formats.

9.3.12.1 Serial Interface Control and Timing

The I²S mode is set by writing to register 0x04.

9.3.12.1.1 I²S Timing

I²S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × f_S is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused trailing data bit positions.

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 56. I²S 64-f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 57. I²S 48-f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 58. I²S 32-f_S Format

9.3.12.1.2 Left-Justified

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × f_S is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions.

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 59. Left-Justified 64-f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 60. Left-Justified 48-f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 61. Left-Justified 32-f_S Format

9.3.12.1.3 Right-Justified

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × f_S is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions.

Figure 62. Right Justified 64-f_S Format

Figure 63. Right Justified 48-f_S Format

Figure 64. Right Justified 32-f_S Format

9.3.13 DirectPath Headphone/Line Driver

The TAS5721 device has a stereo output which can be used as a line driver or a headphone driver that can output 2-Vrms stereo. An audio system can be set up for different applications using this device.

9.3.13.1 Using Headphone Amplifier in TAS5721

The device can be represented as shown in Figure 65: analog inputs (single-ended) as DR_INA (pin 7) and DR_INB (pin 10) with the outputs DR_OUTA (pin 8) and DR_OUTB (pin 9).

Figure 65. Headphone/Line Driver with Analog Input

DR_SD pin can be used to turn ON or OFF the headphone amplifier and line driver.

Speaker channels are independent of headphone and line driver in this mode.

9.3.13.2 Using Line Driver Amplifier in TAS5721

Single-supply headphone and line driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 66 illustrates the conventional line driver amplifier connection to the load and output signal.

DC blocking capacitors for headphone amps are often large in value, and a mute circuit is needed during power up to minimize click and pop for both headphone and line driver. The output capacitors and mute circuits consume PCB area and increase cost of assembly, and can reduce the fidelity of the audio output signal.

Figure 66. Conventional and DirectPath HP and Line Driver

The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail.

Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode.

The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail, combining this with the built in click and pop reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors.

The bottom block diagram and waveform of Figure 66 illustrate the ground-referenced headphone and line driver architecture. This is the architecture of the TAS5721.

9.4.1 Output Mode and MUX Selection

The TAS5721 is a highly configurable device, capable of operating in 2.0, Single Device 2.1 and parallel bridge tied load (PBTL) configurations. Addtionally, the modulation scheme can be changed for the channels to operate either in AD or BD Modulation mode. While many configurations are possible because of this flexibility, the majority of use cases uses will operate in one of the configurations shown below. For ease of use and reduced complexity, the figure below outlines both the register settings and the output configurations required to set the device up for operation in these various modes.

The output configuration quick reference table below highlights the controls that are required to configure the device for various operational modes. Please note that other controls, which are not directly related to the output configuration muxes may also be required. For example, the Inter Channel Delay (ICD) settings will likely need to be modified to optimize for idle channel noise, cross-talk, and distortion performance for each of these considerations, in addition to start and stop time and others. Please consult the respective registers for these controls to optimize for various other performance parameters and use cases.

Table 1. Output Configuration Quick Reference

OUTPUT CONFIGURATION	MODULATION MODE	REGISTER SETTINGS	BLOCK DIAGRAM
2.0 (Stereo BTL)	AD for Both Outputs	0x20[23] = 0 0x20[19] = 0 0x20[15:8] = 0x77 0x05[7] = 0 0x05[2] = 0 0x25[23:8] = 0x0213 0x1A[7:0] = 0x0F
	BD for Both Outputs	0x20[23] = 1 0x20[19] = 1 0x20[15:8] = 0x77 0x05[7] = 0 0x05[2] = 0 0x25[23:8] = 0x0213 0x1A[7:0] = 0x0A
Single Device 2.1 (Stereo Single Ended + Mono BTL) Note: In these described configurations, the polarity of the signal being sent to SPK_OUTB is inverted. For this reason, care should be taken to ensure that the speakers are connected as shown in the block diagram.	AD for Both SE Outputs AD for Single BTL Output	0x20[23] = 0 0x20[19] = 0 0x20[3] = 0 0x05[7] = 1 0x05[2] = 1 0x25[23:8] = 0x0132 0x1A[7:0] = 0x95 0x20[7:4] = 0x7 0x21[8] = 0 0x20[25] = 1
	AD for both SE Outputs BD for Single BTL Output	0x20[23] = 0 0x20[19] = 0 0x20[3] = 1 0x05[7] = 1 0x05[2] = 1 0x25[23:8] = 0x0132 0x1A[7:0] = 0x95 0x20[7:4] = 0x7 0x21[8] = 0 0x20[25] = 1
1.0 Mono PBTL	AD	0x05[7] = 0 0x05[5] = 0 0x05[2] = 0 0x19[7:0] = 0x3A 0x1A[7:0] = 0x0F 0x20[23] = 0 0x20[15:12] = 0x7 0x25[23:8] = 0x0123
	BD	0x05[7] = 0 0x05[5] = 0 0x05[2] = 0 0x19[7:0] = 0x3A 0x1A[7:0] = 0x0A 0x20[23] = 1 0x20[15:12] = 0x7 0x25[23:8] = 0x0123

9.5.1 General I²C Operation

The I²C bus employs two signals to communicate between integrated circuits in a system: (data) SDA and (clock) SCL. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 67. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5721 holds SDA low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals through a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.

Figure 67. Typical I²C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 67.

Pin ADR/FAULT defines the I²C device address. An external 15-kΩ pull down on this pin gives a device address of 0x34 and a 15-kΩ pull up gives a device address of 0x36. The 7-bit address is 0011011 (0x36) or 0011010 (0x34).

9.5.2 26-Bit 3.23 Number Format

All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23 numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown in Figure 68.

Figure 68. 3.23 Format

The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 68. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 69 applied to obtain the magnitude of the negative number.

Figure 69. Conversion Weighting Factors—3.23 Format to Floating Point

Gain coefficients, entered via the I²C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 70.

Figure 70. Alignment of 3.23 Coefficient in 32-Bit I²C Word

Table 4. Serial Control Interface Register Summary

9.6.1 Clock Control Register (0x00)

The clocks and data rates are automatically determined by the TAS5721. The clock control register contains the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The device accepts a 64 f_S or 32 f_S SCLK rate for all MCLK ratios, but accepts a 48 f_S SCLK rate for MCLK ratios of 192 f_S and 384 f_S only.

9.6.2 Device ID Register (0x01)

The device ID register contains the ID code for the firmware revision

9.6.3 Error Status Register (0x02)

The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors.

Error Definitions:

• MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK Error: The number of SCLKs per LRCLK is changing.
• LRCLK Error: LRCLK frequency is changing.
• Frame Slip: LRCLK phase is drifting with respect to internal frame sync.

9.6.4 System Control Register 1 (0x03)

The system control register 1 has several functions:

9.6.5 Serial Data Interface Register (0x04)

As shown in Table 9, the TAS5721 supports nine serial data modes. The default is 24-bit, I²S mode,

9.6.6 System Control Register 2 (0x05)

When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute).

9.6.7 Soft Mute Register (0x06)

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).

9.6.8 Volume Registers (0x07, 0x08, 0x09, 0x0A)

Step size is 0.5 dB

9.6.9 Volume Configuration Register (0x0E)

9.6.10 Modulation Limit Register (0x10)

The modulation limit is the maximum duty cycle of the PWM output waveform. It is important to note that for any applications with PVDD greater than 18 V, the maximum modulation index must be set to 93.8%.

9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)

Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

The ICD settings have high impact on audio performance (for example, dynamic range, THD+N, crosstalk, and so forth). Therefore, appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD mode, then update these registers before coming out of all-channel shutdown.

9.6.12 Pwm Shutdown Group Register (0x19)

Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D6 in the system control register.

This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D6 is set to 0 in system control register 2, 0x05).

9.6.13 Start/stop Period Register (0x1A)

This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times are only approximate and vary depending on device activity level and I²S clock stability.

9.6.14 Oscillator Trim Register (0x1B)

The TAS5721 PWM processor contains an internal oscillator to support autodetect of I²S clock rates. This reduces system cost because an external reference is not required. TI recommends a reference resistor value of that shown in the Typical Application Diagrams. The circuit that uses this resistor should be calibrated or trimmed after each time the device is reset.

Writing 0x00 to register 0x1B enables the trim that was programmed at the factory. It is important to note that after writing the value 0x00 to the trim register, the register will repor the value 0xC0, to indicate the trim process is complete.

9.6.15 BKND_ERR Register (0x1C)

When a backend error signal is received from the internal power stage, the power stage is reset stopping all PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 19 before attempting to restart the power stage.

9.6.16 Input Multiplexer Register (0x20)

This register controls the modulation scheme (AD or BD mode) as well as the routing of I²S audio to the internal channels.

9.6.17 Channel 4 Source Select Register (0x21)

This register selects the channel 4 source.

9.6.18 PWM Output MUX Register (0x25)

This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin.

Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03.
See Table 22 for details.

9.6.19 DRC Control (0x46)

Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default.

9.6.20 Bank Switch and EQ Control (0x50)

The bank switching feature is described in detail in section Bank Switching.

All DAP coefficients are 3.23 format unless specified otherwise.