ZHCSUT0D October 2001 – February 2024 TFP410
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | DE_GEN | VS_POL | HS_POL | Reserved | DE_DLY[8] | ||
| Bit | Field | Type | Description |
|---|---|---|---|
| 7 | Reserved | R/W | — |
| 6 | DE_GEN | R/W | This read/write register enables the internal DE generator. 0: DE generator is disabled. Signal required on DE pin 1: DE generator is enabled. DE pin is ignored. |
| 5 | VS_POL | R/W | This read/write register sets the VSYNC polarity. 0: VSYNC is considered active low. 1: VSYNC is considered active high. Line counts are reset on the VSYNC active edge. |
| 4 | HS_POL | R/W | This read/write register sets the HSYNC polarity. 0: HSYNC is considered active low. 1: HSYNC is considered active high. Pixel counts are reset on the HSYNC active edge. |
| 1:3 | Reserved | R/W | — |
| 0 | DE_DLY[8] | R/W | This read/write register contains the top bit of DE_DLY. |