ZHCSEP3B February   2016  – February 2016 THS3217

PRODUCTION DATA.  

1. 1 特性
2. 2 應用
3. 3 說明
4. 4 修訂歷史記錄
5. 5 Device Comparison Table
6. 6 Pin Configuration and Functions
7. 7 Specifications
   1. 7.1  Absolute Maximum Ratings
   2. 7.2  ESD Ratings
   3. 7.3  Recommended Operating Conditions
   4. 7.4  Thermal Information
   5. 7.5  Electrical Characteristics: D2S
   6. 7.6  Electrical Characteristics: OPS
   7. 7.7  Electrical Characteristics: D2S + OPS
   8. 7.8  Electrical Characteristics: Midscale (DC) Reference Buffer
   9. 7.9  Typical Characteristics: D2S + OPS
   10. 7.10 Typical Characteristics: D2S Only
   11. 7.11 Typical Characteristics: OPS only
   12. 7.12 Typical Characteristics: Midscale (DC) Reference Buffer
   13. 7.13 Typical Characteristics: Switching Performance
   14. 7.14 Typical Characteristics: Miscellaneous Performance
8. 8 Parameter Measurement Information
   1. 8.1 Overview
   2. 8.2 Frequency Response Measurement
   3. 8.3 Harmonic Distortion Measurement
   4. 8.4 Noise Measurement
   5. 8.5 Output Impedance Measurement
   6. 8.6 Step-Response Measurement
   7. 8.7 Feedthrough Measurement
   8. 8.8 Midscale Buffer ROUT Versus CLOAD Measurement
9. 9 Detailed Description
   1. 9.1 Overview
   2. 9.2 Functional Block Diagram
   3. 9.3 Feature Description
      1. 9.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2-V/V (Pins 2, 3, 6 and 14)
      2. 9.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)
      3. 9.3.3 Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)
         1. 9.3.3.1 Output DC Offset and Drift for the OPS
         2. 9.3.3.2 OPS Harmonic Distortion (HD) Performance
         3. 9.3.3.3 Switch Feedthrough to the OPS
         4. 9.3.3.4 Driving Capacitive Loads
      4. 9.3.4 Digital Control Lines
   4. 9.4 Device Functional Modes
      1. 9.4.1 Full-Signal Path Mode
         1. 9.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage
         2. 9.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage
         3. 9.4.1.3 External Connection
      2. 9.4.2 Dual-Output Mode
      3. 9.4.3 Differential I/O Voltage Mode
10. 10Application and Implementation
    1. 10.1 Application Information
       1. 10.1.1 Typical Applications
          1. 10.1.1.1 High-Frequency, High-Voltage, Dual-Output Line Driver for AWGs
             1. 10.1.1.1.1 Design Requirements
             2. 10.1.1.1.2 Detailed Design Procedure
             3. 10.1.1.1.3 Application Curves
          2. 10.1.1.2 High-Voltage Pulse-Generator
             1. 10.1.1.2.1 Design Requirements
             2. 10.1.1.2.2 Detailed Design Procedure
             3. 10.1.1.2.3 Application Curves
          3. 10.1.1.3 Single-Supply, AC-Coupled, Piezo Element Driver
             1. 10.1.1.3.1 Design Requirements
          4. 10.1.1.4 Output Common-Mode Control Using the Midscale Buffer as a Level Shifter
             1. 10.1.1.4.1 Design Requirements
          5. 10.1.1.5 Differential I/O Driver With independent Common-Mode Control
             1. 10.1.1.5.1 Design Requirements
11. 11Power Supply Recommendations
    1. 11.1 Thermal Considerations
12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
13. 13器件和文檔支持
    1. 13.1 器件支持
       1. 13.1.1 開發(fā)支持
          1. 13.1.1.1 TINA-TI（免費軟件下載）
    2. 13.2 文檔支持
       1. 13.2.1 相關(guān)文檔
    3. 13.3 社區(qū)資源
    4. 13.4 商標
    5. 13.5 靜電放電警告
    6. 13.6 Glossary
14. 14機械、封裝和可訂購信息