9.2.1.1 Design Requirements

To show achievable performance with a high performance SAR ADC, the THS5432 is tested as the drive amplifier for the ADS8321. The ADS8321 is a 16-bit, SAR ADC that offers excellent AC and DC performance, with ultra-low power and small size. The circuit shown in Figure 87 is used to test the performance. Data was taken using the ADS8321 at 100 kSPS with input frequency of 10 kHz and signal levels 0.5 dB below full scale. The FFT plot of the spectral performance is in Figure 88. A summary of the FFT analysis results are in Table 6 along with ADS8321 typical data sheet performance at f_S = 100 kSPS. Refer to its data sheet for more information.

9.2.1.2 Detailed Design Procedure

The standard ADS8321 EVM and THS5432 EVM are modified to implement the schematic in Figure 87 and used to test the performance of the THS5432 as a drive amplifier. With single supply +5-V supply the output common-mode of the THS5432 defaults to +2.5 V as required at the input of the ADS8321 so the V_OCM input of the THS5432 simply bypassed to GND with 0.22-µF capacitor. The summary of results of the FFT analysis versus typical data sheet performance shown in Table 6 show that the THS5432 will make an excellent drive amplifier for this ADC.

9.2.1.3 Application Curve

Figure 88. THS5432 + ADS8321 1-kHz FFT

9.2.2.1 Design Requirements

To show achievable performance with a high performance audio ADC, the THS5432 is tested as the drive amplifier for the PCM4204. The PCM4204 is a high-performance, four-channel analog-to-digital converter (ADC) designed for professional and broadcast audio applications. The PCM4204 architecture uses a 1-bit delta-sigma modulator per channel incorporating an advanced dither scheme for improved dynamic performance, and supports PCM output data. The PCM4204 provides flexible serial port interface and many other advanced features. Refer to the PCM4204 data sheet for more information. Figure 89 shows the circuit.

9.2.2.2 Detailed Design Procedure

The PCM4204 EVM is used to test the audio performance of the THS5432 as a drive amplifier. The standard PCM4204 EVM is provided with 4x OPA1632 fully-differential amplifiers, which use the same pin out as the THS5432. For testing, one of these amplifiers is replaced with a THS5432 device in same package (MSOP), gain changed to 1 V/V, and power supply changed to single supply 5 V. With single supply +5-V supply the output common-mode of the THS5432 defaults to 2.5 V as required at the input of the PCM4204. So the resistor connecting the V_OCM input of the THS5432 to the input common-mode drive from the PCM4204 is optional and no performance change was noted with it connected or removed. The EVM power connections were modified by connecting positive supply inputs, 15 V, 5 VA, and 5 VD, to a 5-V external power supply (EXT 3.3 was not used) and connecting –15 V and all ground inputs to ground on the external power supply so only one external 5-V supply was needed to power all devices on the EVM.

An audio analyzer is used to provide an analog audio input to the EVM and the PCM formatted digital output is read by the digital input on the analyzer. Data was taken at f_S = 96 kHz, and audio output uses PCM format. Other data rates and formats are expected to show similar performance in line with that shown in the data sheet.

9.2.2.3 Application Curves

Figure 90 shows the THD+N vs Frequency with no weighting and Figure 91 shows an FFT with 1-kHz input tone. Input signal to the PCM4204 for these tests is –0.5 dBFS. Table 7 summarizes results of testing using the THS5432 + PCM4204 versus typical Data Sheet performance, and show it make an excellent drive amplifier for this ADC.

Figure 90. THS5432 + PCM4204 THD+N vs Frequency With No Weighting

Figure 91. THS5432 + PCM4204 1-kHz FFT

9.2.3.1 Design Requirements

To show achievable performance with a high performance SAR ADC, the THS5432 is tested as the drive amplifier for the ADS7945. The ADS7945 is a 14-bit, SAR ADC that offers excellent AC and DC performance, with low power and small size. The circuit shown in Figure 92 is used to test the performance. Data was taken using the ADS7945 at 2MSPS with input frequency of 10 kHz and signal level 0.5 dB below full scale. The FFT plot of the spectral performance is in Figure 93. A summary of the FFT analysis results are in Table 8 along with ADS7945 typical data sheet performance at f_S = 2 MSPS. Refer to the data sheet for more information.

9.2.3.2 Detailed Design Procedure

The standard ADS7945 EVM and THS5432 EVM are modified to implement the schematic in Figure 92 and used to test the performance of the THS5432 as a drive amplifier. With single supply 5 V supply the output common-mode of the THS5432 defaults to +2.5 V as required at the input of the ADS7945 so the V_OCM input of the THS5432 simply bypassed to GND with 0.22-µF capacitor. The summary of results of the FFT analysis versus typical data sheet performance shown in Table 8 show that the THS5432 will make an excellent drive amplifier for this ADC.

9.2.3.3 Application Curve

Figure 93. THS5432 and ADS7945 Test Circuit

9.3.1.1 AC-Coupled, Differential-Input to Differential-Output Design Issues

There are two typical ways to use the THS5432 family with an AC-coupled differential source. In the first method, the source is differential and can be coupled in through two blocking capacitors. The second method uses either a single-ended or a differential source and couples in through a transformer (or balun). Figure 95 shows a typical blocking capacitor approach to a differential input. An optional differential-input termination resistor (R_M) is included in this design. This R_M element allows the input R_G resistors to be scaled up while still delivering lower differential input impedance to the source. In this example, the R_G elements sum to show a 500-Ω differential impedance, while the R_M element combines in parallel to give a net 100-Ω, AC-coupled, differential impedance to the source. Again, the design proceeds ideally by selecting the R_F element values, then the R_G to set the differential gain, then an R_M element (if needed) to achieve the target input impedance. Alternatively, the R_M element can be eliminated, the R_G elements set to the desired input impedance, and R_F set to the get the differential gain (R_F / R_G).

Figure 95. Example Down-Converting Mixer Delivering an AC-Coupled Differential Signal to the THS5432

The DC biasing here is very simple. The output V_OCM is set by the input control voltage; and because there is no DC-current path for the output common-mode voltage, that DC bias also sets the input pins common-mode operating points.

9.3.2.1 Input Impedance

The designs so far have included a source impedance, R_S, that must be matched by R_T and R_G1. The total impedance at the junction of R_T and R_G1 for the circuit of Figure 99 is the parallel combination of R_T to ground, and the ZA (active impedance) presented by R_G1. The expression for ZA, assuming R_G2 is set to obtain the differential divider balance, is given by Equation 5:

Equation 5.

For designs that do not need impedance matching, for instance where the input is driven from the low-impedance output of another amplifier, R_G1 = R_G2 is the single-to-differential design used without an R_T to ground. Setting R_G1 = R_G2 = R_G in Equation 5 produces Equation 6, which is the input impedance of a simple-input FDA driven from a low-impedance, single-ended source.

Equation 6.

In this case, setting a target gain as R_F / R_G ≡ α, and then setting the desired input impedance allows the R_G element to be resolved first. Then the R_F is set to get the target gain. For example, targeting an input impedance of 200 Ω with a gain of 4 V/V, Equation 7 calculates the R_G value. Multiplying this required R_G value by a gain
of 4 gives the R_F value and the design of Figure 96.

Equation 7.

Figure 96. 200-Ω Input Impedance, Single-Ended to Differential DC-Coupled Design With Gain of 4 V/V

After being designed, this circuit can also be AC-coupled by adding blocking caps in series with the two 120-Ω R_G resistors. This active input impedance has the advantage of increasing the apparent load to the prior stage using lower resistors values, leading to lower output noise for a given gain target.

9.3.3.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion

When the signal path can be AC-coupled, the DC biasing for the THS5432 family becomes a relatively simple task. In all designs, start by defining the output common-mode voltage. The AC-coupling issue can be separated for the input and output sides of an FDA design. The input can be AC-coupled and the output DC-coupled, or the output can be ac-coupled and the input dc-coupled, or they can both be AC-coupled.

One situation where the output might be DC-coupled (for an AC-coupled input), is when driving directly into an ADC where the V_OCM control voltage uses the ADC common-mode reference to directly bias the FDA output common-mode to the required ADC input common-mode. In any case, the design starts by setting the desired V_OCM.

When an AC-coupled path follows the output pins, the best linearity is achieved by operating V_OCM at midsupply. The V_OCM voltage must be within the linear range for the common-mode loop, as specified in the headroom specifications (approximately 0.91 V greater than the negative supply and 1.1 V less than the positive supply). If the output path is also ac-coupled, simply letting the V_OCM control pin float is usually preferred to get a midsupply default V_OCM bias with minimal elements. To limit noise, place a 0.1-µF decoupling capacitor on the V_OCM pin to ground.

After V_OCM is defined, check the target output voltage swing to ensure that the V_OCM plus the positive and negative output swing on each side do not clip into the supplies. If the desired output differential swing is defined as V_OPP, divide by 4 to obtain the ±V_P swing around V_OCM at each of the two output pins (each pin operates 180° out of phase with the other). Check that V_OCM ±V_P does not exceed the absolute supply rails for this rail-to-rail output (RRO) device.

Going to the device input pins side, because both the source and balancing resistor on the nonsignal input side are DC-blocked (see Figure 98), no common-mode current flows from the output common-mode voltage, thus setting the input common-mode equal to the output common-mode voltage.

This input headroom also sets a limit for higher V_OCM voltages. Because the input V_ICM is the output V_OCM for ac-coupled sources, the 1.2-V minimum headroom for the input pins to the positive supply overrides the 1.1-V headroom limit for the output V_OCM. Also, the input signal moves this input V_ICM around the dc bias point, as described in the section Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA.

Figure 98. AC-Coupled, Single-Ended Source to a Differential Gain of 2 V/V Test Circuit

9.3.3.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion

The output considerations remain the same as for the AC-coupled design. Again, the input can be DC-coupled while the output is AC-coupled. A DC-coupled input with an AC-coupled output might have some advantages to move the input V_ICM down if the source is ground referenced. When the source is DC-coupled into the THS5432 family (see Figure 99), both sides of the input circuit must be DC-coupled to retain differential balance. Normally, the nonsignal input side has an R_G element biased to whatever the source midrange is expected to be. Providing this midscale reference gives a balanced differential swing around V_OCM at the outputs.

Often, R_G2 is simply grounded for DC-coupled, bipolar-input applications. This configuration gives a balanced differential output if the source is swinging around ground. If the source swings from ground to some positive voltage, grounding R_G2 gives a unipolar output differential swing from both outputs at V_OCM (when the input is at ground) to one polarity of swing. Biasing R_G2 to an expected midpoint for the input signal creates a differential output swing around V_OCM.

One significant consideration for a DC-coupled input is that V_OCM sets up a common-mode bias current from the output back through R_F and R_G to the source on both sides of the feedback. Without input balancing networks, the source must sink or source this DC current. After the input signal range and biasing on the other R_G element is set, check that the voltage divider from V_OCM to V_IN through R_F and R_G (and possibly R_S) establishes an input V_ICM at the device input pins that is in range.

If the average source is at ground, the negative rail input stage for the THS5432 family is in range for applications using a single positive supply and a positive output V_OCM setting because this DC current lifts the average FDA input summing junctions up off of ground to a positive voltage (the average of the V+ and V– input pin voltages on the FDA).

Figure 99. DC-Coupled, Single-Ended-to-Differential, Set for a Gain of 5 V/V 

9.3.3.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA

The design equations for setting the resistors around an FDA to convert from a single-ended input signal to differential output can be approached from several directions. Here, several critical assumptions are made to simplify the results:

• The feedback resistors are selected first and set equal on the two sides.
• The DC and AC impedances from the summing junctions back to the signal source and ground (or a bias voltage on the nonsignal input side) are set equal to retain feedback divider balance on each side of the FDA.

Both of these assumptions are typical for delivering the best dynamic range through the FDA signal path.

After the feedback resistor values are chosen, the aim is to solve for the R_T (a termination resistor to ground on the signal input side), R_G1 (the input gain resistor for the signal path), and R_G2 (the matching gain resistor on the nonsignal input side); see Figure 98 and Figure 99. The same resistor solutions can be applied to either AC- or DC-coupled paths. Adding blocking capacitors in the input-signal chain is a simple option. Adding these blocking capacitors after the R_T element (as shown in Figure 98) has the advantage of removing any DC currents in the feedback path from the output V_OCM to ground.

Earlier approaches to the solutions for R_T and R_G1 (when the input must be matched to a source impedance, R_S) follow an iterative approach. This complexity arises from the active input impedance at the R_G1 input. When the FDA is used to convert a single-ended signal to differential, the common-mode input voltage at the FDA inputs must move with the input signal to generate the inverted output signal as a current in the R_G2 element. A more recent solution is shown as Equation 8, where a quadratic in R_T can be solved for an exact value. This quadratic emerges from the simultaneous solution for a matched input impedance and target gain. The only inputs required are:

• The selected R_F value.
• The target voltage gain (A_v) from the input of R_T to the differential output voltage.
• The desired input impedance at the junction of R_T and R_G1 to match R_S.

Solving this quadratic for R_T starts the solution sequence, as shown in Equation 8:

Equation 8.

Being a quadratic, there are limits to the range of solutions. Specifically, after R_F and R_S are chosen, there is physically a maximum gain beyond which Equation 8 starts to solve for negative R_T values (if input matching is a requirement). With R_F selected, use Equation 9 to verify that the maximum gain is greater than the desired gain.

Equation 9.

If the achievable A_V(MAX) is less than desired, increase the R_F value. After R_T is derived from Equation 8, the R_G1 element is given by Equation 10:

Equation 10.

Then, the simplest approach is to use a single R_G2 = R_T || R_S + R_G1 on the nonsignal input side. Often, this approach is shown as the separate R_G1 and R_S elements. Using these separate elements provides a better divider match on the two feedback paths, but a single R_G2 is often acceptable. A direct solution for R_G2 is given as Equation 11:

Equation 11.

This design proceeds from a target input impedance matched to R_S, signal gain A_v from the matched input to the differential output voltage, and a selected R_F value. The nominal R_F value chosen for the THS5432 family characterization is 2 kΩ. As discussed previously, going lower improves noise and phase margin, but reduces the total output load impedance possibly degrading harmonic distortion. Going higher increases the output noise, and might reduce the loop-phase margin because of the feedback pole to the input capacitance, but reduces the total loading on the outputs.

Using Equation 9 to Equation 11 to sweep the target gain from 1 to A_V(MAX) < 10 V/V gives Table 9, which shows exact values for R_T, R_G1, and R_G2, where a 50-Ω source must be matched while setting the two feedback resistors to 2 kΩ. One possible solution for 1% standard values is shown, and the resulting actual input impedance and gain with % errors to the targets are also shown in Table 9.

These equations and design flow apply to any FDA. Using the feedback resistor value as a starting point is particularly useful for current-feedback-based FDAs such as the LMH6554, where the value of these feedback resistors determines the frequency response flatness. Similar tables can be built using the equations provided here for other source impedances, R_F values, and gain ranges.

The TINA model correctly shows this actively-set input impedance in the single-ended to differential configuration, and is a good tool to validate the gains, input impedances, response shapes, and noise issues.