This section includes information on the various configuration options available with the TLK10x. The configuration options described below include:

3.1 Bootstrap Configuration

Bootstrap configuration is a convenient way to configure the TLK10x into specific modes of operation. Some of the functional pins are used as configuration inputs. The logic states of these pins are sampled during reset and are used to configure the device into specific modes of operation. The table below describes bootstrap configuration.

A 2.2kΩ resistor is used for pull-down or pull-up to change the default configuration. If the default option is desired, then there is no need for external pull-up or pull down resistors. Because these pins may have alternate functions after reset is deasserted, they must not be connected directly to VCC or GND.

3.2 Power Supply Configuration

The TLK10x provides best-in-class flexibility of power supplies.

3.2.1 Single Supply Operation

If a single 3.3V power supply is desired, the TLK10x internal regulator provides the necessary core supply voltages. Ceramic capacitors of 10µf and 0.1µf should be placed close to the PFBOUT (pin 15) which is the output of the internal regulator. The PFBOUT pin should be connected to the PFBIN1 and PFBIN2 on the board. A small capacitor of 0.1µF should be placed close to the PFBIN1 (pin 13) and PFBIN2 (pin 24). To operate in this mode, connect the TLK10x supply pins as shown in Figure 3-1.

Figure 3-1 Power Connections for Single Supply Operation

3.2.2 Dual Supply Operation

When a 1.55V external power rail is available, the TLK10x can be configured as shown in Figure 3-2. PFBOUT (pin 15) is left floating. The 1.55V external supply is connected to PFBIN1 (pin 13) and PFBIN2 (pin 24). Furthermore, to lower the power consumption, the internal regulator should be powered down by writing ‘1’ to bit 15 of the VRCR register (0x00d0h).

Figure 3-2 Power Connections for Dual Supply Operation

When operating with dual supplies, follow these guidelines:

• When powering up, ramp up the 3.3V supply before the 1.55V supply.
• When powering down, turn off the 1.55V supply before turning off the 3.3V supply.
• Use the external RESET pin after power up to reset the PHY.
• To use the internal power-on reset, PFBIN1 and PFBIN2 must be operational less than 100ms after 3.3V rises to detect the internal RESET.

3.3 IO Pins Hi-Z State During Reset

The following IO or output pins are in hi-Z state when RESET is active (Low).

3.4 Auto-Negotiation

The TLK10x device auto-negotiates to operate in 10Base-T or 100Base-TX. With Auto-Negotiation enabled, the TLK10x negotiates with the link partner to determine the speed and duplex mode. If the link partner cannot Auto-Negotiate, the TLK10x device enters parallel-detect mode to determine the speed of the link partner. Parallel-detect mode uses fixed half-duplex mode.

The TLK10x supports four different Ethernet protocols (10Mbs Half-Duplex, 10Mbs Full-Duplex, 100Mbs Half-Duplex, and 100Mbs Full-Duplex). Auto-Negotiation selects the highest performance protocol based on the advertised ability of the Link Partner. Control the Auto-Negotiation function within the TLK10x by internal register access according to the IEEE specification.

Alternatively, control the HD-FD functionality by configuring the AN_0 pins. The state of AN_0 selects full or half duplex mode, both in Auto-negotiation or force 100/10 mode as given in Table 3-2. The state of AN_0 upon power-up/reset, determines the state of bits [8:5] of the ANAR register (0x04h).

Auto-Negotiation advertises ANEN, 100BT by default. Full-Duplex or Half-Duplex configuration is available through the AN_0 bit. Internal register access configures the device for a specific mode.

Internal register access controls the Auto-Negotiation function, as defined by the IEEE 802.3u specification. For further detail regarding Auto-Negotiation, see Clause 28 of the IEEE 802.3u specification.

3.5 Auto-MDIX

The TLK10x device automatically determines whether or not it needs to cross over between pairs, eliminating the requirement for an external crossover cable. If the TLK10x interoperates with a device that implements MDI/MDIX crossover, a random algorithm as described in IEEE 802.3 determines which device performs the crossover.

Auto-MDIX is enabled by default and can be configured via pin strap, control register CR1 (0x09h), bit 14 or via register PHYCR (0x19h), bit 15.

The crossover can be manually forced through bit 14 of the PHYCR (0x19h) register. Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs.

Auto-MDIX can be used in the forced 100Base-TX mode. Because in modern networks all the nodes are 100Base-TX, having the Auto-MDIX working in the forced 100Base-TX mode resolves the link faster without the need for the long Auto-Negotiation period.

3.6 MII Isolate Mode

The TLK10x can be put into MII-Isolate mode by writing bit 10 of the BMCR register.

When in the MII-Isolate mode, the TLK10x ignores packet data present at the TXD[3:0], TX_EN inputs, and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in isolate mode, the TLK10x continues to respond to all management transactions.

When in isolate mode, the PMD output pair does not transmit packet data, but continues to source 100Base-TX scrambled idles or 10Base-T normal link pulses. The TLK10x can auto-negotiate or parallel detect on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the TLK10x is in Isolate mode.

3.7 PHY Address

The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown in Table 3-3.

Each TLK10x or port sharing an MDIO bus in a system must have a unique physical address. With 5 address input pins, the TLK10x can support PHY Address values 0 (<00000>) through 31 (<11111>). The address-pin states are latched into an internal register at device power-up and hardware reset. Because all the PHYAD[4:0] pins have weak internal pull-down/up resistors, the default setting for the PHY address is 00001 (0x01h).

See Figure 3-3 for an example of a PHYAD connection to external components. In this example, the PHYAD configuration results in address 00011 (0x03h).

Figure 3-3 Illustrative PHYAD Configuration Example

3.8 LED Interface

The TLK10x supports one configurable Light Emitting Diode (LED) pin. The device supports 2 LED configurations: Link and Activity. Functions are multiplexed into two modes. The LED can be controlled by configuration pin and internal register bits. Bit 5 of the PHY Control register (PHYCR) selects the LED mode as described in Table 3-4.

The LED_LINK pin in Mode 1 indicates the link status of the port. The LED is OFF when no link is present. In Mode 2 it is ON to indicate that the link is good; BLINK indicates that activity is present on either transmit or receive channel. Bits 10:9 of the LEDCR register (0x18) control the blink rate. The default blink rate is 5Hz. Enabling Enhanced LED Link via the CR2 register (0x0A) bit 4 overrides the LED blinking functionality of the PHYCR register (0x0019) bit 5. The Link LED will not blink for activity when Enhanced LED Link is enabled.

See Figure 3-4 for an example of AN_0 connections to external components. In this example, the configuration results in Full-Duplex advertised.

Figure 3-4 AN Pin Configuration and LED Loading Example

3.9 Loopback Functionality

The TLK10x provides several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK10x digital and analog data path. Generally, the TLK10x may be configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback.

3.9.1 Near-End Loopback

Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or analog circuitry. The point at which the signal is looped back is selected using loopback control bits with several options being provided. Figure 3-5 shows the PHY near-end loopback functionality.

Figure 3-5 Block Diagram, Near-End Loopback Mode

The Near-end Loopback mode is selected by setting the respective bit in the BIST Control Register (BISCR), MII register address 0x0016. MII loopback can be selected by using the BMCR register at address 0x0000, bit [14].

The Near-end Loopback can be selected according to the following:

• Reg 0x0000, Bit [14]: MII Loopback
• Reg 0x0016, Bit [0]: PCS input Loopback
• Reg 0x0016, Bit [1]: PCS output Loopback
• Reg 0x0016, Bit [2]: Digital Loopback
• Reg 0x0016, Bit [3]: Analog Loopback

Table 3-5 describes the available operational modes for each loop mode:

Table 3-5 Loop Modes

LOOP MODE	MII	PCS INPUT	PCS OUTPUT	DIGITAL	ANALOG(1)	EXTERNAL
Operational Setting	Force/ANEG 100/10	Force 100/10	Force 100	Force 100	Force 10/100 ANEG 10	Force/ANEG 100/10
Operational MAC int.	MII Only	MII or RMII	MII or RMII	MII or RMII	MII or RMII	MII or RMII

(1) Requires 100Ω termination

While in MII Loopback mode, there is no link indication, but packets propagate back to the MAC. While in MII Loopback mode the data is looped back, and can also be transmitted onto the media. For transmitting data during MII loopback in 100BT only please use bit [6] in the BISCR Register address 0x0016. For proper operation in Analog Loopback mode, attach 100Ω terminations to the RJ45 connector. External Loopback can be performed while working in normal mode (Bits 3:0 of the BISCR register are asserted to 0, and on the RJ45 connector, pin 1 is connected to pin 3 and pin 2 is connected to pin 6). To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting Loopback mode. This constraint does not apply for external-loopback mode. For selected loopback Delay propagation timing please see Section 9.9.21.

3.9.2 Far-End Loopback

Far-end (Reverse) loopback is a special test mode to allow testing the PHY from the link-partner side. In this mode, data that is received from the link partner passes through the PHY's receiver, looped back on the MII and transmitted back to the link partner. Figure 3-6 shows Far-end loopback functionality.

Figure 3-6 Block Diagram, Far-End Loopback Mode

The Reverse Loopback mode is selected by setting bit 4 in the BIST Control Register (BISCR), MII register address 0x0016.

While in Reverse Loopback mode the data is looped back and also transmitted onto the MAC Interface and all data signals that come from the MAC are ignored.

Table 3-6 describes the operating modes for Far-End Loopback.

Table 3-6 Far-End Loopback Modes

OPERATIONAL MAC INT.	MII MODE	RMII MODE
Operational Setting	Force/ANEG 10/100	Force/ANEG 10

3.10 BIST

The device incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. The BIST can be performed using both internal loopback (digital or analog) or external loopback using a cable fixture. The BIST simulates pseudo-random data transfer scenarios in format of real packets and Inter-Packet Gap (IPG) on the lines. The BIST allows full control of the packet lengths and of the IPG.

The BIST is implemented with independent transmit and receive paths, with the transmit block generating a continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for the BIST. The received data is compared to the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The number of error bytes that the PRBS checker received is stored in the BICSR1 register (0x001Bh). The status of whether the PRBS checker is locked to the incoming receive bit stream, whether the PRBS has lost sync, and whether the packet generator is busy, can be read from the BISCR register (0x0016h). While the lock and sync indications are required to identify the beginning of proper data reception, for any link failures or data corruption, the best indication is the contents of the the error counter in the BICSR1 register (0x001Bh).

The PRBS test can be put in a continuous mode or single mode by using bit 14 of the BISCR register (0x0016h). In continuous mode, when one of the PRBS counters reaches the maximum value, the counter starts counting from zero again. In single mode, when the PRBS counter reaches its maximum value, the PRBS checker stops counting.

The device allows the user to control the length of the PRBS packet. By programming the BICSR2 register (0x001Ch) one can set the length of the PRBS packet. There is also an option to generate a single-packet transmission of two types, 64 and 1518 bytes, through register bit 13 of the BISCR register (0x0016h). The single generated packet is composed of a constant data.

3.11 Cable Diagnostics

With the vast deployment of Ethernet devices, the need for reliable, comprehensive and user-friendly cable diagnostic tool is more important than ever. The wide variety of cables, topologies, and connectors deployed results in the need to non-intrusively identify and report cable faults. The TI cable-diagnostic unit provides extensive information about cable integrity.

The TLK10x offers the following capabilities in its Cable Diagnostic tools kit:

1. Time Domain Reflectometry (TDR)
2. Active Link Cable Diagnostic (ALCD)