7.4.1 Shutdown Mode

The TPL0102 can be put in Shutdown Mode by executing the proper command in the ACR (Access Control Register). Please see the TPL0102 Register Map for more details. When active, this feature causes terminal H to become high impedance.

Figure 18. Equivalent Circuit for Shutdown Mode

7.4.2 Voltage Divider Mode

The digital potentiometer generates a voltage divider when all three terminals are used. The voltage divider at wiper-to-H and wiper-to-L is proportional to the input voltage at H to L.

Figure 19. Equivalent Circuit for Voltage Divider Mode

For example, connecting terminal H to 5 V and terminal L to ground, the output voltage at terminal W can range from 0 V to 5 V. The general equation defining the output voltage at terminal W for any valid input voltage applied to terminal H and terminal L is

Equation 1.

The voltage difference between terminal H and terminal W can also be calculated

Equation 2.

where

• D is the decimal value of the wiper code.

7.4.3 Rheostat Mode

The TPL0102 operates in rheostat mode when only two terminals are used as a variable resistor. The variable resistance can either be between terminal H and terminal W or between terminal L and terminal W.  The unused terminal can be left floating or it can be tied to terminal W. The nominal resistance between terminal H and terminal L is 100 kΩ and has 256 tap points accessed by the wiper terminal. The 8-bit volatile register value is used to determine one of the 256 possible wiper positions.

In rheostat mode, to set the resistance between terminal H and terminal W, the potentiometer can be configured in two possible ways.

Figure 20. Equivalent Circuit for Rheostat Mode with Terminal H to Terminal W Resistance

The general equation for determining the digitally programmed output resistance between Terminal H and Terminal W is:

Equation 3.

where

• R_TOT is the end-to-end resistance between terminal H and terminal L.
• D is the decimal value of the wiper code.

Similarly, to set the resistance between terminal L and terminal W, the potentiometer can be configured in two possible ways.

Figure 21. Equivalent Circuit for Rheostat Mode with Terminal L to Terminal W Resistance

The general equation for determining the digitally programmed output resistance between terminal L and terminal W is

Equation 4.

where

• R_TOT is the end-to-end resistance between terminal H and terminal L.
• D is the decimal value of the wiper code.

The following table shows the ideal values for DPOT with End-to End resistance of 100 kΩ. The absolute values of resistance can vary significantly but the Ratio (R_WL/R_HW) is extremely accurate.

The linearity values are "relative" linearity values (i.e. linearity after zero-scale and full-scale offset errors are removed). Please take this into account when expecting a certain absolute accuracy since some error will be introduced once you get close in magnitude to the offset errors.

7.5.1 I²C General Operation

7.5.1.2 START and STOP Conditions

I²C communication with this device is initiated by the master sending a START condition and terminated by the master sending a STOP condition. A high-to-low transition on the SDA line while the SCL is high defines a START condition. A low-to-high transition on the SDA line while the SCL is high defines a STOP condition.

Figure 22. Definition of START and STOP Conditions

7.5.1.3 Data Validity and Byte Formation

One data bit is transferred during each clock pulse of the SCL. One byte is comprised of eight bits on the SDA line. A byte may either be a device address, register address, or data written to or read from a slave.

Data is transferred Most Significant Bit (MSB) first. Any number of data bytes can be transferred from the master to slave between the START and STOP conditions. Data on the SDA line must remain stable during the high phase of the clock period, as changes in the data line when the SCL is high are interpreted as control commands (START or STOP).

Figure 23. Definition of Byte Formation

Figure 24. Example use of ACK

When the SDA line remains high during the ACK/NACK-related clock period, this is a NACK signal. There are several conditions that lead to the generation of a NACK:

• The receiver is unable to receive or transmit because it is performing some real-time function and is not ready to start communication with the master.
• During the transfer, the receiver gets data or commands that it does not understand.
• During the transfer, the receiver cannot receive any more data bytes.
• A master-receiver is done reading data and indicates this to the slave through a NACK.

Figure 25. Example use of NACK

7.5.2 I²C Write and Read Operation

7.5.2.2 Write Operation

Figure 26. Write Operation to One or Multiple Registers

7.5.2.4 Read Operation

Figure 27. Read Operation from One Register

Figure 28. Read Operation from Multiple Registers

7.6.1 Slave Address

The device (slave) address can be configured by the user with 3 bits (A2, A1, and A0), allowing for 8 different possibilities for the device address. Please see the Figure 30 for an example.

Figure 29. Device Address in Context with START and ACK

Figure 30 shows an example of how to configure A2, A1 and A0 to give unique device addresses on the same I²C bus. When a bit is wired to Vcc, this gives that bit a value of 1. When a bit is wired to GND, this gives that bit a value of 0.

For example, Device 1 could be the TPL0102 on the I²C bus, which would have a 7 bit device address of 1010 110. There are some interfaces that will require the device address to be inputted in hex. In order to make the device address 8 bits for hex notation, a leading 0 is added to the left of the 7 bit device address. For Device 1, the 8 bit device address is 0101 0110 (0x56h). Device 2 would have a 7 bit device address of 1010 100, which with a leading 0 results in an 8 bit device address of 0101 0100 (0x54h). Device 3 would have a 7 bit device address of 1010 011, and with a leading 0 results in an 8 bit device address of 0101 0011 (0x53h).

Figure 30. Examples of Device Address Configuration on I²C Bus

7.6.2 TPL0102 Register Map

• When writing the entire register map using auto increment, general purpose registers in the register address map need to be written with dummy bytes. The general purpose registers do not effect the outputs of the potentiometers.
• As stated in the Overview, the VOL bit from the ACR (Access Control Register) provides two options for register accessibility. Either only volatile registers (WR) are accessible to change the wiper setting without storing the value in non-volatile memory or volatile registers (WR) and non-volatile registers (IVR) are accessible to change the wiper setting, which allows the value to be stored in non-volatile memory.
• The respective non-volatile and volatile registers have the same register address, thus to write to both the volatile and non-volatile locations, only one register address needs to be entered and the VOL bit needs to be configured properly.

7.6.3 IVRA (Initial Value Register for Potentiometer A)

• Non-volatile register to store wiper position for potentiometer A
• Register will hold value even when device is powered down

7.6.4 WRA (Wiper Resistance Register for Potentiometer A)

• Volatile register to change wiper position for potentiometer A
• IVRA loads value to WRA to determine wiper position

7.6.5 IVRB (Initial Value Register for Potentiometer B)

• Non-volatile register to store wiper position for potentiometer B
• Register will hold value even when device is powered down

7.6.6 WRB (Wiper Resistance Register for Potentiometer B)

• Volatile register to change wiper position for potentiometer B
• IVRB loads value to WRB to determine wiper position

7.6.7 ACR (Access Control Register)

• Volatile register to control register access, determine shut-down mode, and read non-volatile write operations