9.1.1 System-Level ESD Protection

System-level ESD (per EN61000-4-2) may occur as the result of a cable being plugged in, or a user touching the USB connector or cable. Figure 37 shows an example ESD protection for the VBUS path that helps protect the VBUS pin, ISNS and DSCG pins of the device from system-level ESD. The device has ESD protection built into the CC1 and CC2 pins so that no external protection is necessary. Refer to the Layout Guidelines section for external component placement and routing recommendations.

The Schottky diode is to protect against VBUS being drawn below ground by an inductive load, the cable inductance may be as high as 900 nH.

Figure 37. VBUS ESD Protection

9.1.2 Use of GD Internal Clamp

As described in the Configuring Power Capabilities (PSEL, PCTRL, HIPWR) section, the GD pin has an internal clamp. Figure 38 shows an example of how it may be used. V_OUT is the voltage from a power supply that is to be provided onto the VBUS wire of the USB Type-C cable through an NFET resistor. If V_OUT drops, the NFET should be automatically disabled by the device. This can be accomplished by tying the GD pin to V_OUT via a resistor.

The internal resistance of the GD pin is specified to exceed R_(GD), and the input threshold is V_{(GD_TH)}. The GD pin would therefore draw no more than V_{(GD_TH) max} / R_{(GD) min} < 603 nA. As an example, assume the minimum value of V_OUT for which GD should be high is 4.5 V, then the resistor between GD and V_OUT may not exceed (4.5 – V_{(GD_TH) max}) / 603e-9 = 4.5 MΩ. To make it robust against board leakage a smaller resistor such as 1 MΩ can be chosen, but the smaller the resistance the more leakage current into the GD pin. In this example, when V_OUT is 25 V, the current into the GD pin is (25-V_(GDC)) / 1e6 < 1.85 µA.

Figure 38. Use of GD Internal Clamp

9.1.3 Resistor Divider on GD for Programmable Start Up

Figure 39 shows an alternative usage of the GD pin can help protect against shorts on the VBUS pin in the receptacle. A resistor divider is used to minimize the time it takes the GD pin to be pulled low. Consider the situation where the VBUS pin is shorted at startup. At some point, the device closes the NFET switch to supply 5 V to VBUS. At that point, the short pulls down on the voltage seen at the VPWR pin. With the resistor values shown in Figure 39, once the voltage at the VPWR pin reaches 3.95 V the voltage at the GD pin is specified to be below V_{(GD_TH) min}. Without the 700-kΩ resistor, the voltage at the VPWR pin would have to reach V_{(GD_TH) min} which takes longer. This comes at the expense of increased leakage current.

Figure 39. Programmable GD Turn On

The GD resistor values can be calculated using the following process. First, calculate the smallest R_(GD1) that should be used to prevent the internal clamp current from exceeding I_(GD) of 80 µA. For a 20 V advertised voltage, the OVP trip point could be as high as 24 V. Using V_{(GDC) min} = 6.5 V and V_OUT = V_{(FOVP20) max} = 24 V, provides Equation 3:

Equation 3.

The actual clamping current is less than 80 µA as some current flows into R_(GD2). Next, R_(GD2) can be calculated as shown in Equation 4:

Equation 4.

where

• V_(VPWR) = V_{(VPWR_TH)} falling (max) and V_{(GD_TH)} = V_{(GD_TH)} falling (min).

9.1.4 Selection of the CTL1 and CTL2 Resistors (R_(FBL1) and R_(FBL2))

R_(FBL1) and R_(FBL2) provide a means to change the power supply output voltage when switched in by the CTL1 and CTL2 open drain outputs, respectively. When 12 V is requested by the UFP then CTL2 will go low and place R_(FBL2) in parallel with R_(FBL). When 20 V is requested by the UFP then CTL2 remains low and CTL1 goes low placing R_(FBL1) in parallel with R_(FBL2) and R_(FBL).

Figure 40. Circuit to Change V_OUT Upon Sink/UFP Request

R_(FBL2) is calculated using Equation 5. In this example, V_OUT12 is 12 V and V_OUT20 is 20 V. V_OUT is the default output voltage (5 V) for the regulator and is set by R_(FBU), R_(FBL) and error amplifier V_REF.

Equation 5.

R_(FBL1) is calculated using Equation 6 after a standard 1% value for R_(FBL2) is chosen.

Equation 6.

R_(FBL1) and R_(FBL2) should be large enough so that the CTL1 and CTL2 sinking current is minimized (< 1 mA). The sinking current for CTL1 and CTL2 is V_REF / R_(FBL1) and V_REF/R_(FBL2) respectively.

9.1.5 Voltage Transition Requirements

During VBUS voltage transitions, the slew rate (v_SrcSlewPos) must be kept below 30 mV/µs in all portions of the waveform, settle (t_SrcSettle) in less than 275 ms, and be ready (t_SrcReady) in less than 285 ms. For most power supplies, these requirements are met naturally without any special circuitry but in some cases, the voltage transition ramp rate must be slowed in order to meet the slew rate requirement.

The requirements for linear voltage transitions are shown in Table 7. In all cases, the minimum slew time is below 1 ms.

When transition slew control is required, the interaction of the slew mechanism and dc/dc converter loop response must be considered. A simple R-C filter between the device CTL pins and converter feedback node may lead to instability under some conditions. Figure 41 shows a method which manages the slew control without adding capacitance to the converter feedback node.

Figure 41. Slew-Rate Control Example No. 1

When V_OUT = 5 V, both CTL1 and CTL2 are in a high impedance state. When a 5 V to 12 V transition is requested, CTL2 goes low and turns off Q_(CTL2). Q_(SL2) gate starts to rise towards VCC at a rate determined by R_(SL2A) + R_(SL2B) and C_(SL2). Q_(SL2) gate continues to rise, until Q_(SL2) is fully enhanced placing R_(FBL2) in parallel with R_(FBL). In similar fashion when C_(TL1) goes low, Q_(CTL1) turns off allowing R_(FBL1) to slew in parallel with R_(FBL2) and R_(FBL).

The slewing resistors and capacitor can be chosen using the following equations. V_T is the VGS threshold voltage of Q_(SL1) and Q_(SL2). V_REF is the feedback regulator reference voltage. Choose the slewing resistance in the 100 kΩ range to reduce the loading on the bias voltage source (VCC) and then calculate C_(SL). The falling transitions is shorter than the rising transitions in this topology.

Falling transitions:

• 20 V to 12 V

Equation 7.

• 12 V to 5 V

Equation 8.

Rising transitions:

• 5 V to 12 V

Equation 9.

• 12 V to 20 V

Equation 10.

Some converter regulators can tolerate a balance of capacitance on the feedback node without affecting loop stability. The LM5175 has been tested using Figure 42 to combine V_OUT slewing with a minimal amount of extra circuitry.

Figure 42. Slew-Rate Control Example No. 2

When a higher voltage is requested from TPS25740, CTL1 or CTL2 goes low changing the sensed voltage at the FB pin. The LM5175 compensates by increasing C_(SLU). As V_OUT increases, C_(SLU) is charged at a rate proportional to R_(FBU). Three time constants yields a voltage change of approximately 95% and can be used to calculate the desired slew time. C_(SLU) can be calculated using Equation 11 and Equation 12.

Equation 11.

Equation 12.

In order to minimize loop stability effects, a capacitor in parallel with R_(FBL) is required. The ratio of C_(SLU)/C_(SLL) should be chosen to match the ratio of R_(FBL)/R_(FBU). Choose C_(SLL) according to Equation 13.

Equation 13.

All slew rate control methods should be verified on the bench to ensure that the slew rate requirements are being met when the external VBUS capacitance is between 1 μF and 100 μF.

9.1.6 V_BUS Slew Control using GDNG C_(SLEW)

Care should be taken to control the slew rate of Q1 using C_(SLEW); particularly in applications where C_OUT >> C_(SLEW). The slew rate observed on VBUS when charging a purely capacitive load is the same as the slew rate of V_(GDNG) and is dominated by the ratio I_(GDNON) / C_(SLEW). R_(SLEW) helps block C_(SLEW) from the GDNG pin enabling a faster transient response to OCP.

Figure 43. Slew-Rate control Using GDNG

There may be fault conditions where the voltage on VBUS triggers an OVP condition and then remains at a high voltage even after the TPS25740 configures the voltage source to output 5 V via CTL1 and CTL2. When this OVP occurs, the TPS25740 opens Q1 within t_FOVP + t_FOVPDG. The TPS25740 then issues a hard reset, discharge the power-path via the R_(DSCG), and waits for 795 ms before enabling Q1 again. Due to the fault condition the voltage again triggers an OVP event when the voltage on VBUS exceeds V_(FOVP). This retry process would continue as long as the fault condition persists, periodically pulsing up to V_(FOVP) + V_SrcSlewPos x (t_FOVP + t_FOVPDG) onto the VBUS of the Type-C receptacle. It is recommended to use a slew rate less than the maximum of V_SrcSlewPos (30 mV / µs) allowed by USB (refer to 文檔支持), the slew rate should instead be set in order to meet the requirement to have the voltage reach the target voltage within t_SrcSettle (275 ms). This also limits the out-rush current from the C_OUT capacitor into the C_(PDIN) capacitor and help protect Q1 and R_S.

9.1.7 Tuning OCP Using R_F and C_F

In applications where there are load transients or moderate ripple on V_OUT, the OCP performance of TPS25740 or TPS25740A may be impacted. Adding the R_F/C_F filter network as shown in Figure 44 helps mitigate the impact of the ripple and load transients on OCP performance.

Figure 44. ISNS Filtering Example

R_F/C_F can be tailored to the amount of ripple on V_OUT as shown in Table 8.

9.2.1 Design Requirements

9.2.2 Detailed Design Procedure

9.2.3 Application Curves

DFP End - VBUS = 5 V

Figure 46. Load Regulation

DFP End - VBUS = 20 V

Figure 48. Load Regulation

No Load

Figure 50. VBUS 5 V – 12 V Transition

No Load

Figure 52. VBUS 12 V – 20 V Transition

No Load

Figure 54. VBUS 5 V – 20 V Transition

DFP End - VBUS = 12 V

Figure 47. Load Regulation

No Load

Figure 49. VBUS Startup

No Load

Figure 51. VBUS 12 V – 5 V Transition

No Load

Figure 53. VBUS 20 V – 12 V Transition

No Load

Figure 55. VBUS 20 V – 5 V Transition

9.2.4 Typical Application, D/C Power Source

In this design example the PSEL pin is configured such that P_(SEL) = 65 W (see Table 10). Voltages offered are 5 V, 9 V, and 15 V at a maximum of 3 A. The overcurrent protection (OCP) trip point is set just above 3 A and VDD on the TPS25740A is grounded. The following example is based on TPS25740AEVM-741 (refer to 文檔支持).

Figure 56. DC Power Source

9.2.4.3 Application Curves

No Load

Figure 57. VBUS 5 V – 9 V Transition

No Load

Figure 59. VBUS 9 V – 15 V Transition

No Load

Figure 61. VBUS 5 V – 15 V Transition

No Load

Figure 58. VBUS 9 V – 5 V Transition

No Load

Figure 60. VBUS 15 V – 9 V Transition

No Load

Figure 62. VBUS 15 V – 5 V Transition

9.3.1 D/C Power Source (Power Hub)

In this system design example, the P_(SEL) is configured such that P_(SEL) = 93 W and 5 V, 12 V or 20 V are offered at a maximum of 5 A. The over-current protection (OCP) trip point is set just above 5 A.

Figure 63. Power Hub Concept (Provider only)

This power hub circuit takes a 24 V input and produces a regulated output voltage. The over-current protection feature in the TPS25740 is not used; the ISNS and VBUS pins are connected directly. Instead R_(ILIM) is chosen to set the current limit of the TPS40170 synchronous PWM buck controller. If the current limit trips, the GD pin of the TPS25740 is pulled low by the PGOOD pin of the TPS40170, which causes the power-path switch to be opened. Other fault conditions may also pull PGOOD low, but the slew rate of the voltage transition should be controlled as in one of the examples given above (Figure 41, Figure 42, or Figure 43).

VDD on the TPS25740 is grounded, if there is a suitable power supply available in the system the TPS25740 operates more efficiently if it is connected to VDD since V_(VPWR) > V_(VDD). See Figure 66 for an example.

9.3.2 A/C Power Source (Wall Adapter)

In this system design example, the PSEL pin is configured such that P_(SEL) = 36 W, and only 5 V and 12 V are offered at a maximum of 3 A. The overcurrent protection (OCP) trip point is set just above 3 A. VDD on the TPS25740 is grounded, if there is a suitable power supply available in the system the TPS25740 operates more efficiently if it is connected to VDD since V_(VPWR) > V_(VDD).

Figure 64. Adapter Provider Concept

9.3.3 Dual-Port Power Managed A/C Power Source (Wall Adaptor)

In this system design example, the PSEL pin is configured such that P_(SEL) = 36 W, and only 5 V and 12 V are offered at a maximum of 3 A. The over-current protection (OCP) trip point is set just above 3 A.

The UFP pin from one TPS25740 is attached to the PCTRL pin on the other TPS25740. When one port is not active (no UFP attached through the receptacle) its UFP pin is left high-z so the PCTRL pin on the other port is pulled high. This allows the adaptor to provide up to the full 36 W on a single port if a single UFP is attached. If two UFP’s are attached (one to each port) then each port only offers current that would reach a maximum of 18 W. So each port is allocated half of the overall power when each port has a UFP attached.

Figure 65. Dual-Port Adapter Provider Concept

9.3.4 D/C Power Source (Power Hub with 3.3 V Rail)

In Figure 66, an LDO that outputs at least I_(SUPP) at 3.3 V or 5 V is added to the power hub concept, and the DVDD pin is used to enable the buck regulator since it is active high. For an active low buck regulator, the UFP pin could be used. This implementation is more power efficient than the one in Figure 63.

Figure 66. Power Hub Concept (Provider only)