SLVSC16B August 2013 – July 2016 TPS43330A-Q1
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4
Device Functional Modes
- 7.4.1
Buck Controllers: Normal Mode PWM Operation
- 7.4.1.1 Frequency Selection and External Synchronization
- 7.4.1.2 Enable Inputs
- 7.4.1.3 Feedback Inputs
- 7.4.1.4 Soft-Start Inputs
- 7.4.1.5 Current-Mode Operation
- 7.4.1.6 Current Sensing and Current Limit With Foldback
- 7.4.1.7 Slope Compensation
- 7.4.1.8 Power-Good Outputs and Filter Delays
- 7.4.1.9 Light-Load PFM Mode
- 7.4.1
Buck Controllers: Normal Mode PWM Operation
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Boost Component Selection
- 8.2.2.2 Boost Maximum Input Current IIN_MAX
- 8.2.2.3 Boost Inductor Selection, L
- 8.2.2.4 Inductor Ripple Current, IRIPPLE
- 8.2.2.5 Peak Current in Low-Side FET, IPEAK
- 8.2.2.6 Right Half-Plane Zero RHP Frequency, fRHP
- 8.2.2.7 Output Capacitor, COUTx
- 8.2.2.8 Bandwidth of Boost Converter, fC
- 8.2.2.9 Output Ripple Voltage Due to Load Transients, ?VOUTx
- 8.2.2.10 Selection of Components for Type II Compensation
- 8.2.2.11 Input Capacitor, CIN
- 8.2.2.12 Output Schottky Diode D1 Selection
- 8.2.2.13 Low-Side MOSFET (BOT_SW3)
- 8.2.2.14 BuckA Component Selection
- 8.2.2.15 Inductor Selection L
- 8.2.2.16 Inductor Ripple Current IRIPPLE
- 8.2.2.17 Output Capacitor COUTA
- 8.2.2.18 Bandwidth of Buck Converter fC
- 8.2.2.19 Selection of Components for Type II Compensation
- 8.2.2.20 Resistor Divider Selection for Setting VOUTA Voltage
- 8.2.2.21 BuckB Component Selection
- 8.2.2.22 Resistor Divider Selection for Setting VOUT Voltage
- 8.2.2.23 BuckX High-Side and Low-Side N-Channel MOSFETs
- 8.2.3 Application Curves
- 8.3 System Examples
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DAP|38
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DAP|38
訂購信息
6 Specifications
6.1 Absolute Maximum Ratings(1)
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Voltage | Input voltage: VIN, VBAT | –0.3 | 60 | V | |
| Voltage (buck function: BuckA and BuckB) |
Ground: PGNDA–AGND, PGNDB–AGND | –0.3 | 0.3 | V | |
| Enable inputs: ENA, ENB | –0.3 | 60 | |||
| Bootstrap inputs: CBA, CBB | –0.3 | 68 | |||
| Bootstrap inputs: CBA–PHA, CBB–PHB | –0.3 | 8.8 | |||
| Phase inputs: PHA, PHB | –0.7 | 60 | |||
| Phase inputs: PHA, PHB (for 150 ns) | –1 | 60 | |||
| Feedback inputs: FBA, FBB | –0.3 | 13 | |||
| Error-amplifier outputs: COMPA, COMPB | –0.3 | 13 | |||
| High-side MOSFET drivers: GA1-PHA, GB1-PHB | –0.3 | 8.8 | |||
| Low-side MOSFET drivers: GA2–PGNDA, GB2–PGNDB | –0.3 | 8.8 | |||
| Current-sense voltage: SA1, SA2, SB1, SB2 | –0.3 | 13 | |||
| Soft start: SSA, SSB | –0.3 | 13 | |||
| Power-good outputs: PGA, PGB | –0.3 | 13 | |||
| Power-good delay: DLYAB | –0.3 | 13 | |||
| Switching-frequency timing resistor: RT | –0.3 | 13 | |||
| SYNC, EXTSUP | –0.3 | 13 | |||
| Voltage (boost function) |
Low-side MOSFET driver: GC1–PGNDA | –0.3 | 8.8 | V | |
| Error-amplifier output: COMPC | –0.3 | 13 | |||
| Enable input: ENC | –0.3 | 13 | |||
| Current-limit sense: DS | –0.3 | 60 | |||
| Output-voltage select: DIV | –0.3 | 8.8 | |||
| Voltage (PMOS driver) |
P-channel MOSFET driver: GC2 | –0.3 | 60 | V | |
| P-channel MOSFET driver: VIN-GC2 | –0.3 | 8.8 | |||
| Voltage (Gate-driver supply) | Gate-driver supply: VREG | –0.3 | 8.8 | V | |
| Temperature | Junction temperature: TJ | –40 | 150 | °C | |
| Operating temperature: TA | –40 | 125 | |||
| Storage temperature: Tstg | –55 | 165 | |||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to AGND, unless otherwise specified.
6.2 ESD Ratings
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
| Charged-device model (CDM), per AEC Q100-011 | All pins except 1, 19, 20, and 38 | ±500 | |||
| Pins 1, 19, 20, and 38 | ±750 | ||||
| Machine model | All pins except 15 and 24 | ±200 | |||
| Pins 15 and 24 | ±150 | ||||
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Buck function: BuckA and BuckB voltage |
Input voltage: VIN, VBAT | 4 | 40 | V |
| Enable inputs: ENA, ENB | 0 | 40 | ||
| Boot inputs: CBA, CBB | 4 | 48 | ||
| Phase inputs: PHA, PHB | –0.6 | 40 | ||
| Current-sense voltage: SA1, SA2, SB1, SB2 | 0 | 11 | ||
| Power-good output: PGA, PGB | 0 | 11 | ||
| SYNC, EXTSUP | 0 | 9 | ||
| Boost function | Enable input: ENC | 0 | 9 | V |
| Voltage sense: DS | 40 | |||
| DIV | 0 | VREG | ||
| Operating temperature: TA | –40 | 125 | °C | |
6.4 Thermal Information
| THERMAL METRIC(1) | TPS4333x-Q1 | UNIT | |
|---|---|---|---|
| DAP (HTSSOP) | |||
| 38 PINS | |||
| RθJA | Junction-to-ambient thermal resistance(2) | 27.3 | °C/W |
| RθJCtop | Junction-to-case (top) thermal resistance(3) | 19.6 | °C/W |
| RθJB | Junction-to-board thermal resistance(4) | 15.9 | °C/W |
| ψJT | Junction-to-top characterization parameter(5) | 0.24 | °C/W |
| ψJB | Junction-to-board characterization parameter(6) | 6.6 | °C/W |
| RθJCbot | Junction-to-case (bottom) thermal resistance(7) | 1.2 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7)
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88
6.5 DC Electrical Characteristics
VIN = 8 V to 18 V, TJ = –40°C to +150°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| INPUT SUPPLY | ||||||||
| VBAT | Supply voltage | Boost controller enabled, after satisfying initial start-up condition | 2 | 40 | V | |||
| VIN | Input voltage required for device on initial start-up | 6.5 | 40 | V | ||||
| Buck regulator operating range after initial start-up | 4 | 40 | ||||||
| VIN(UV) | Buck undervoltage lockout | VIN falling. After a reset, initial start-up conditions may apply.(3) | 3.5 | 3.6 | 3.8 | V | ||
| VIN rising. After a reset, initial start-up conditions may apply.(3) | 3.8 | 4 | ||||||
| VBOOST_UNLOCK | Boost unlock threshold | VBAT rising | 8.2 | 8.5 | 8.8 | V | ||
| IQ_LPM | LPM quiescent current(1) | VIN = 13 V, TA = 25°C | BuckA: LPM, BuckB: off | 30 | 40 | µA | ||
| BuckB: LPM, BuckA: off | ||||||||
| BuckA, B: LPM, | 35 | 45 | ||||||
| VIN = 13 V, TA = 125°C | BuckA: LPM, BuckB: off | 40 | 50 | µA | ||||
| BuckB: LPM, BuckA: off | ||||||||
| BuckA, B: LPM, | 45 | 55 | ||||||
| IQ_NRM | Quiescent current: normal (PWM) mode(1) |
SYNC = HIGH, TA = 25°C, VIN = 13 V | BuckA: CCM, BuckB: off | 4.85 | 5.3 | mA | ||
| BuckB: CCM, BuckA: off | ||||||||
| BuckA, B: CCM | 7 | 7.6 | ||||||
| SYNC = HIGH, TA = 125°C, VIN = 13 V | BuckA: CCM, BuckB: off | 5 | 5.5 | mA | ||||
| BuckB: CCM, BuckA: off | ||||||||
| BuckA, B: CCM | 7.5 | 8 | ||||||
| Ibat_sh | Shutdown current | BuckA, B: off, VBAT = 13 V | TA = 25°C | 2.5 | 4 | µA | ||
| TA = 125°C | 3 | 5 | µA | |||||
| VINLPMexit | VIN level to exit LPM | VIN falling | 7.7 | 8 | 8.3 | V | ||
| VINLPMentry | VIN level to enable entering LPM | VIN rising | 8.2 | 8.5 | 8.8 | V | ||
| VINLPMhys | Hysteresis | VIN rising or falling | 0.4 | 0.5 | 0.6 | V | ||
| INPUT VOLTAGE VBAT - UNDERVOLTAGE LOCKOUT | ||||||||
| VBAT(UV) | Boost-input undervoltage | VBAT falling. After a reset, initial start-up conditions may apply.(3) | 1.8 | 1.9 | 2 | V | ||
| VBAT rising. After a reset, initial start-up conditions may apply.(3) | 2.4 | 2.5 | 2.6 | |||||
| UVLOHys | Hysteresis | 500 | 600 | 700 | mV | |||
| UVLOfilter | Filter time | 5 | µs | |||||
| INPUT VOLTAGE VIN - OVERVOLTAGE LOCKOUT | ||||||||
| VOVLO | Overvoltage shutdown | VIN rising | 45 | 46 | 47 | V | ||
| VIN falling | 43 | 44 | 45 | |||||
| OVLOHys | Hysteresis | 1 | 2 | 3 | V | |||
| OVLOfilter | Filter time | 5 | µs | |||||
| BOOST CONTROLLER | ||||||||
| Vboost7V | Boost VOUT = 7 V | DIV = low, VBAT = 2 V to 7 V | 6.8 | 7 | 7.3 | V | ||
| Vboost7V-th | Boost-enable threshold | Boost VOUT = 7 V | VBAT falling | 7.5 | 8 | 8.5 | V | |
| Boost-disable threshold | VBAT rising | 8 | 8.5 | 9 | ||||
| Boost hysteresis | VBAT rising or falling | 0.4 | 0.5 | 0.6 | ||||
| Vboost10V | Boost VOUT = 10 V | DIV = open, VBAT = 2 V to 10 V | 9.7 | 10 | 10.4 | V | ||
| Vboost10V-th | Boost-enable threshold | Boost VOUT = 10 V | VBAT falling | 10.5 | 11 | 11.5 | V | |
| Boost-disable threshold | VBAT rising | 11 | 11.5 | 12 | ||||
| Boost hysteresis | VBAT rising or falling | 0.4 | 0.5 | 0.6 | ||||
| Vboost8.85V | Boost VOUT = 8.85 V | DIV = VREG, VBAT = 2 V to 8.85 V | 8.35 | 8.85 | 9.35 | V | ||
| Vboost8.85V-th | Boost-enable threshold | Boost VOUT = 8.85 V | VBAT falling | 9.15 | 9.85 | 10.45 | V | |
| Boost-disable threshold | VBAT rising | 9.65 | 10.35 | 10.85 | ||||
| Boost hysteresis | VBAT rising or falling | 0.4 | 0.5 | 0.6 | ||||
| BOOST-SWITCH CURRENT LIMIT | ||||||||
| VDS | Current-limit sensing | DS input with respect to PGNDA | 0.175 | 0.2 | 0.225 | V | ||
| tDS | Leading-edge blanking | 200 | ns | |||||
| GATE DRIVER FOR BOOST CONTROLLER | ||||||||
| IGC1 Peak | Gate-driver peak current | 1.5 | A | |||||
| rDS(on) | Source and sink driver | VREG = 5.8 V, IGC1 current = 200 mA | 2 | Ω | ||||
| GATE DRIVER FOR PMOS | ||||||||
| rDS(on) | PMOS OFF | 10 | 20 | Ω | ||||
| IPMOS_ON | Gate current | VIN = 13.5 V, VGS = –5 V | 10 | mA | ||||
| tdelay_ON | Turnon delay | C = 10 nF | 5 | 10 | µs | |||
| BOOST-CONTROLLER SWITCHING FREQUENCY | ||||||||
| fsw-Boost | Boost switching frequency | fSW_Buck / 2 | kHz | |||||
| DBoost | Boost duty cycle | 90% | ||||||
| ERROR AMPLIFIER (OTA) FOR BOOST CONVERTERS | ||||||||
| GmBOOST | Forward transconductance | VBAT = 12 V | 0.8 | 1.35 | mS | |||
| VBAT = 5 V | 0.35 | 0.65 | ||||||
| BUCK CONTROLLERS | ||||||||
| VBuckA or VBuckB | Adjustable output-voltage range | 0.9 | 11 | V | ||||
| Vref, NRM | Internal reference and tolerance voltage in normal mode | Measure FBX pin | 0.792 | 0.8 | 0.808 | V | ||
| –1% | 1% | |||||||
| Vref, LPM | Internal reference and tolerance voltage in low-power mode | Measure FBX pin | 0.784 | 0.8 | 0.816 | V | ||
| –2% | 2% | |||||||
| Vsense | V sense for forward-current limit in CCM | Measured across Sx1 and Sx2, FBx = 0.75 V (low duty-cycle) |
60 | 75 | 90 | mV | ||
| V sense for reverse-current limit in CCM | Measured across Sx1 and Sx2, FBx = 1 V | –65 | –37.5 | –23 | ||||
| VI-Foldback | V sense for output short | Measured across Sx1 and Sx2, FBx = 0 V | 17 | 32.5 | 48 | mV | ||
| tdead | Shoot-through delay, blanking time | 20 | ns | |||||
| DCNRM | High-side minimum ON-time | 100 | ns | |||||
| Maximum duty cycle (digitally controlled) | 98.75% | |||||||
| DCLPM | Duty cycle, LPM | 80% | ||||||
| ILPM_Entry | LPM entry-threshold load current as fraction of maximum set load current | 1% | .(2) | |||||
| ILPM_Exit | LPM exit-threshold load current as fraction of maximum set load current | See(2) | 10% | |||||
| HIGH-SIDE EXTERNAL NMOS GATE DRIVERS FOR BUCK CONTROLLER | ||||||||
| IGX1_peak | Gate-driver peak current | 1.5 | A | |||||
| rDS(on) | Source and sink driver | VREG = 5.8 V, IGX1 current = 200 mA | 2 | Ω | ||||
| LOW-SIDE NMOS GATE DRIVERS FOR BUCK CONTROLLER | ||||||||
| IGX2_peak | Gate-driver peak current | 1.5 | A | |||||
| RDS ON | Source and sink driver | VREG = 5.8 V, IGX2 current = 200 mA | 2 | Ω | ||||
| ERROR AMPLIFIER (OTA) FOR BUCK CONVERTERS | ||||||||
| GmBUCK | Transconductance | COMPA, COMPB = 0.8 V, source/sink = 5 µA, test in feedback loop |
0.72 | 1 | 1.35 | mS | ||
| DIGITAL INPUTS: ENA, ENB, ENC, SYNC | ||||||||
| VIH | Higher threshold | VIN = 13 V | 1.7 | V | ||||
| VIL | Lower threshold | VIN = 13 V | 0.7 | V | ||||
| RIH_SYNC | Pulldown resistance on SYNC | VSYNC = 5 V | 500 | kΩ | ||||
| RIL_ENC | Pulldown resistance on ENC | VENC = 5 V | 500 | kΩ | ||||
| IIL_ENx | Pullup current source on ENA, ENB | VENx = 0 V | 0.5 | 2 | µA | |||
| BOOST OUTPUT VOLTAGE: DIV | ||||||||
| VIH_DIV | Higher threshold | VREG = 5.8 V | VREG – 0.2 | V | ||||
| VIL_DIV | Lower threshold | 0.2 | V | |||||
| Voz_DIV | Voltage on DIV if unconnected | Voltage on DIV if unconnected | VREG / 2 | V | ||||
| INTERNAL GATE-DRIVER SUPPLY | ||||||||
| VREG | Internal regulated supply | VIN = 8 V to 18 V, VEXTSUP = 0 V, SYNC = high | 5.5 | 5.8 | 6.1 | V | ||
| Load regulation | IVREG = 0 mA to 100 mA, VEXTSUP = 0 V, SYNC = high |
0.2% | 1% | |||||
| VREG(EXTSUP) | Internal regulated supply | VEXTSUP = 8.5 V | 7.2 | 7.5 | 7.8 | V | ||
| Load regulation | IEXTSUP = 0 mA to 125 mA, SYNC = High VEXTSUP = 8.5 V to 13 V |
0.2% | 1% | |||||
| VEXTSUP-th | EXTSUP switch-over voltage threshold | IVREG = 0 mA to 100 mA, VEXTSUP ramping positive |
4.4 | 4.6 | 4.8 | V | ||
| VEXTSUP-Hys | EXTSUP switch-over hysteresis | 150 | 250 | mV | ||||
| IVREG-Limit | Current limit on VREG | VEXTSUP = 0 V, normal mode as well as LPM | 100 | 400 | mA | |||
| IVREG_EXTSUP-Limit | Current limit on VREG when using EXTSUP | IVREG = 0 mA to 100 mA, VEXTSUP = 8.5 V, SYNC = High |
125 | 400 | mA | |||
| SOFT START | ||||||||
| ISSx | Soft-start source current | VSSA and VSSB = 0 V | 40 | 50 | 60 | µA | ||
| OSCILLATOR (RT) | ||||||||
| VRT | Oscillator reference voltage | 1.2 | V | |||||
| POWER GOOD / DELAY | ||||||||
| PGth1 | Power-good threshold | FBx falling | –5% | –7% | –9% | |||
| PGhys | Hysteresis | 2% | ||||||
| PGdrop | Voltage drop | IPGA = 5 mA | 450 | mV | ||||
| IPGA = 1 mA | 100 | |||||||
| PGleak | Power-good leakage | VSx2 = VPGx = 13 V | 1 | µA | ||||
| tdeglitch | Power-good deglitch time | 2 | 16 | µs | ||||
| tdelay | Reset delay | External capacitor = 1 nF VBuckX < PGth1 |
1 | ms | ||||
| tdelay_fix | Fixed reset delay | No external capacitor, pin open | 20 | 50 | µs | |||
| IOH | Activate current source (current to charge external capacitor) | 30 | 40 | 50 | µA | |||
| IIL | Activate current sink (current to discharge external capacitor) | 30 | 40 | 50 | µA | |||
| OVERTEMPERATURE PROTECTION | ||||||||
| Tshutdown | Junction-temperature shutdown threshold | 150 | 165 | °C | ||||
| Thys | Junction-temperature hysteresis | 15 | °C | |||||
(1) Quiescent current specification is non-switching current consumption without including the current in the external-feedback resistor divider.
(2) The exit threshold specification is to be always higher than the entry threshold.
(3) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| SWITCHING PARAMETER – BUCK DC-DC CONTROLLERS | |||||||
| fSW_Buck | Buck switching frequency | RT | GND | 360 | 400 | 440 | kHz |
| 60-kΩ external resistor | |||||||
| fSW_adj | Buck adjustable range with external resistor | RT pin: external resistor | 150 | 600 | kHz | ||
| fSYNC | Buck synchronization range | External clock input | 150 | 600 | kHz | ||
6.7 Typical Characteristics
| VIN = 12 V | VOUT = 5 V | fSW = 400 kHz |
| L = 4.7 µH | RSENSE = 10 mΩ |
| VIN = 12 V | VOUT = 5 V | fSW = 400 kHz |
| L = 4.7 µH | RSENSE = 10 mΩ |
0 to 4 A at 2.5 A/µs
| VIN = 12 V | VOUT = 5 V | fSW = 400 kHz |
| L = 4.7 µH | RSENSE = 10 mΩ |
4 A to 90 mA at 2.5 A/µs
| VIN = 10 V | fSW = 200 kHz | |
| L = 1 µH | RSENSE = 7.5 mΩ |
| VIN = 10 V | BuckA 5 V at 1.5 A |
BuckB = 3.3 V at 3.5 A |
| fSW = 200 kHz | L = µH, RSENSE = 7.5 mΩ |
CIN = 440 µF, COUT = 660 µF |
in 1 ms at Buck Outputs 7.5 W and 11.5 W)
| VIN = 12 V | VOUT = 5 V | fSW = 400 kHz |
| L = 4.7 µH | RSENSE = 10 mΩ |
| VIN = 12 V | VOUT = 5 V | fSW = 400 kHz |
| L = 4.7 µH | RSENSE = 10 mΩ |
90 mA to 4 A at 2.5 A/µs
| VBAT = 5 V, VIN = 10 V |
fSW = 200 kHz | L = 680 nH |
| RSENSE = 10 mΩ | CIN = 440 µF | COUT = 660 µF |
(0 A to 5 A at 10 A/µs)
| VIN = 10 V | BuckA = 5 V at 1.5 A |
BuckB = 3.3 V at 3.5 A |
| fSW = 200 kHz | L = 1 µH, RSENSE = 7.5 mΩ |
CIN = 440 µF, COUT = 660 µF |
in 1 ms at Boost Direct Output 25 W)
