7.3.1 Current Sensing

The TPS53632 device provides independent channels of current feedback for every phase. These independent channels increase the system accuracy and reduce the dependence of circuit performance on layout compared to an externally summed architecture. The design can use inductor DCR sensing to yield the best efficiency or resistor current sensing to yield the most accuracy across wide temperature ranges. DCR sensing can be optimized by using a NTC thermistor to reduce the variation of current sense with temperature.

The pins CSP1, CSN1, CSP2, CSN2 and CSP3, CSN3 are the current sensing pins.

7.3.2 Load Transients

When the load increases suddenly, the output voltage immediately drops. This voltage drop is reflected as a rising voltage on the DROOP pin. This rising voltage forces the PWM to pulse sooner and more frequently which causes the inductor current to rapidly increase. As the inductor current reaches the new load current, a steady-state operating condition is reached and the PWM switching resumes the steady-state frequency. Similarly, when the load releases suddenly, the output voltage rises. This rise is reflected as a falling voltage on the COMP pin. This rising voltage forces a delay in the PWM pulses until the inductor current reaches the new load current, when the switching resumes and steady-state switching continues.

7.3.3 AutoBalance™ Current Sharing

The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of each phase to equalize the current in each phase.

The PWM comparator (not shown) starts a pulse when the feedback voltage equals the reference voltage. The VIN voltage charges the C_t(on) capacitor through the resistor R_t(on). The pulse is terminated when the voltage at capacitor C_t(on) matches the on-time (t_ON) reference, normally the DAC voltage (V_DAC).

A current sharing circuit is shown in Figure 13. For example, assume that the 5 µs averaged value of I1 = I2 = I3. In this case, the PWM modulator terminates at V_DAC, and the normal pulse width is delivered to the system. If instead, I1 > I_AVG, then an offset is subtracted from V_DAC, and the pulse width for Phase 1 is shortened, reducing the current in Phase 1 to compensate. If I1 < I_AVG, then a longer pulse is produced, again compensating on a pulse-by-pulse basis.

Figure 13. AutoBalance Current Sharing

7.3.4 PWM and SKIP Signals

The PWM and SKIP signals are outputs of the controller and serve as input to the driver or DrMOS type devices. Both are 5-V logic signals. The PWM signals are logic high when the high-side driver turns ON. The PWM signal must be low for the low-side drive to turn ON. When both the drive signals are OFF, the PWM is in tri-state.

7.3.5 5-V, 3.3-V and 1.8-V Undervoltage Lockout (UVLO)

The TPS53632 device continuously monitors the voltage on the V5A, VDD and VINTF pins to ensure a value high enough to bias the device properly and provide sufficient gate drive potential to maintain high efficiency. The converter starts with a voltage of approximately 4.4 V and has a nominal 200 mV of hysteresis. After the 5VA, VDD or VINTF pins go below the V_UVLOL level, the corresponding voltage must fall below V_POR (1.5 V) to reset the device.

The input voltage (V_VIN) does not include a UVLO function, so the circuit runs with power inputs as low as approximately 3 x V_OUT.

7.3.6 Output Undervoltage Protection (UVP)

Output undervoltage protection works in conjunction with the current protection described in the Overcurrent Protection (OCP) section. If the output voltage drops below the low PGOOD voltage threshold, then the drivers are turned OFF until the EN pin power is cycled.

7.3.7 Overcurrent Protection (OCP)

The TPS53632 device uses a valley current limiting scheme, so the ripple current must be considered. The DC current value at OCP (I_OCP) is the OCP limit value plus half of the ripple current. Current limiting occurs on a phase-by-phase and pulse-by-pulse basis. If the voltage between the CSPx and CSNx pins is above the OCP value, the converter delays the next ON pulse until that voltage difference drops below the OCP limit. For inductor current sensing circuits, the voltage between the CSPx and CSNx pins is the inductor DCR value multiplied by the resistor divider which is part of the NTC compensation network. As a result, a wide range of OCP values can be obtained by changing the resistor divider value. In general, use the highest OCP setting possible with the least attenuation in the resistor divider to provide as much signal to the device as possible. This provides the best performance for all parameters related to current feedback.

In OCP mode, the voltage drops until the UVP limit is reached. Then the converter sets the PGOOD to inactive, and the drivers are turned OFF. The converter remains in this state until the device is reset by the V5A, VDD or VINTF rails.

7.3.8 Overvoltage Protection

An OVP condition is detected when the output voltage is greater than the PGDH voltage, and greater than V_DAC. V_OUT > + V_PGDH greater than V_DAC. In this case, the converter sets PGOOD inactive, and turns ON the drive for the low-side MOSFET. The converter remains in this state until the device is reset by cycling the V5A, VDD or VINTF pin. However, the OVP threshold is blanked much of the time. In order to provide protection to the processor 100% of the time, there is a second OVP level fixed at V_OVPH which is always active. If the fixed OVP condition is detected, the PGOOD are forced inactive and the low-side MOSFETs are tuned ON. The converter remains in this state until the V5A, VDD or VINTF pin is reset.

7.3.9 Analog Current Monitor, IMON and Corresponding Digital Output Current

The TPS53632 device includes a current monitor function. The current monitor supplies an analog voltage, proportional to the load current, on the IMON pin.

The current monitor function is related to the OCP selection resistors. The R_OCP is the resistor between the OCP-I pin and GND and R_CIMON is the resistor between the IMON pin to the OCP-I pin that sets the current monitor gain. Equation 1 shows the calculation for the current monitor gain.

Equation 1.

where

• Σ V_CS is the sum of the DC voltages at the inputs to the current sense amplifiers

To ensure stable current monitor operation and at the same time provide a fast dynamic response, connect a capacitor with a value between 4.7-nF and 10-nF between the IMON pin and GND.

Set the analog current monitor so that at the maximum processor current (I_CC(max)) level, the IMON voltage is 1.7 V. This corresponds to a digital output current value of ‘FF’ in register 03H.

7.3.10 Addressing

The TPS53632 device can be configured for three different base addresses by setting a voltage on the SLEWA pin. Configure a resistor divider on SLEWA from VREF to GND. A resistor between the SLEWA pin and GND sets the slew rate. Once the slew rate resistor is selected, the resistor from the VREF pin to the SLEWA pin can be chosen based on the required base address. For a base address of 0, the VREF to SLEWA resistor can be left open.

7.3.11 I²C Interface Operation

The TPS53632 device includes a slave I²C interface accessed via the SCL (serial clock) and SDA (serial data) pins. The interface sets the base VID value, receives current monitor telemetry, and controls functions described in this section. It operates when EN = low, with the bias supplies in regulation. It is compliant with I²C specification UM10204, Revision 3.0. The characteristics are:

• Addressing
  • 7-bit addressing; address range is 100 0xxx (binary)
  • Last three bits are determined by the SLEWA pin at start-up
• Byte read / byte write protocols only (See figures below)
• Frequency
  • 100 kHz
  • 400 kHz
  • 1 MHz
  • 3.4 MHz
• Logic inputs are 1.8-V logic levels (3.3-V tolerant)

7.3.11.1 Key for Protocol Examples

7.3.11.2 Protocol Examples

The good byte read transaction the controller ACKs and the master terminates with a NAK/stop.

Figure 14. Good Byte Read Transaction

The controller issues a NAK to the read command with an invalid register address.

Figure 15. NAK Invalid Register Address

Figure 16 illustrates a good byte write.

Figure 16. Good Byte Write

The controller issues a NAK to a write command with an invalid register address.

Figure 17. Invalid NAK Register Address

The controller issues a NAK to a write command for the condition of invalid data.

Figure 18. Invalid NAK Register Data

The following master code sequence is executed to enter Hs (3.4-MHz SCL) mode.

Figure 19. Master Code Sequence

7.3.12 Start-Up Sequence

The TPS53632 initializes when all of the supply voltages rise above the UVLO thresholds. This function is also know as a cold boot. The device then reads all of the various settings (such as frequency and overcurrent protection). This process takes less than 1.2 ms. During this time, the VSR pin initializes to the BOOT voltage. The output voltage rises to the voltage select register (VSR) level when the EN pin (enable) goes high. As soon as the BOOT sequence completes, PGOOD is HIGH and the I²C interface can be used to change the voltage select register. The current VSR value is held when EN goes low and returns to a high state This function is also know as a warm boot). The VSR can be changed when EN is low, however, this is not recommended prior to completion of the cold boot process.

7.3.13 Phase Add and Drop Operation

The phase add and phase drop operations are enabled by default in the TPS53632 device. The converter starts up in multi-phase CCM mode and reduces phase count until reaching single phase DCM mode as the load is reduced. This action takes place at a fixed percentage of the OCP level defined in the Electrical Characteristics table. The controller automatically adds phases when the current exceeds the defined percentage of the OCP value.

To disable the automatic phase and drop operation, connect a resistor between the VREF pin and the FREQ-P pin so that the voltage is above the value specified in the parameter table.

7.3.14 Power Good Operation

PGOOD is an open-drain output pin that is designed to be pulled up with an external resistor to a voltage 3.6 V or less. Normal PGOOD operation (exclusive of OC or MAXVID interrupt action) is shown in Figure 20. On initial power-up, a power good status occurs within 6 µs of the DAC reaching its target value. When EN is brought low, the PGOOD pin is also brought low for 250 µs and then is allowed to float. The TPS53632 device pulls down the PGOOD signal when the EN signal subsequently goes high and returns high again within 6 µs of the end of the DAC ramp. The delay period between the EN pin going high and the PGOOD pin going low in this case is less than 1 µs.

Figure 20 shows the power good operation at initial start up and with falling and rising EN.

Figure 20. Power Good Operation

7.3.15 Input Voltage Limits

The number of input phases supported varies with the input voltage. See Table 1 for limits. The minimum input voltage is lower for lower frequency operation and/or lower output voltages.

7.3.16 Fault Behavior

The TPS53632 device has a complete suite of fault detection and protection functions, including input undervoltage lockout (UVLO) on all power inputs, overvoltage and overcurrent limiting and output undervoltage detection. The protection limits are summarized in Table 1. The converter suspends switching when the limits are exceeded and the PGOOD pin goes low. In this state, the fault register 14h is readable. To exit fault protection mode, power must be cycled.

7.4.1 PWM Operation

The Functional Block Diagram and Figure 21 show how the converter operates in continuous conduction mode (CCM).

Figure 21. D-CAP+™ Mode Basic Waveforms

Starting with the condition that the high-side FETs are off and the low-side FETs are on, the summed current feedback (I_SUM) is higher than the error amplifier output (V_COMP). I_CMP falls until it hits V_COMP, which contains a component of the output ripple voltage. The PWM comparator senses where the two waveforms cross and triggers the on-time generator, which generates the internal SW_CLK signal. Each SW_CLK signal corresponds to one switching ON pulse for one phase.

During single-phase operation, every SW_CLK signal generates a switching pulse on the same phase. Also, I_SUM voltage corresponds to a single-phase inductor current only.

During multi-phase operation, the controller distributes the SW_CLK signal to each of the phases in a cycle. Using the summed inductor current and cyclically distributing the ON pulses to each phase automatically gives the required interleaving of 360/n, where n is the number of phases.

7.5.1 Operating Frequency

The resistor between the FREQ-P pin and GND sets the switching frequency. See the Electrical Characteristics table for the resistor settings corresponding to each frequency selection.

7.5.2 Overcurrent Protection (OCP) Level

The resistor from OCP-I to GND sets the OCP level of the CPU channel. See the Electrical Characteristics table for the resistor settings corresponding to each OCP level.

7.5.3 IMON Gain

The resistors from IMON to OCP-I and OCP-I to GND set the DC load current monitor (IMON) gain.

7.5.4 Slew Rate

The SetVID fast slew rate is set by the resistor from SLEWA pin to GND. See the Electrical Characteristics table for the resistor settings corresponding to each slew rate setting.

7.5.5 Base Address

The voltage on SLEWA pin sets the device base address.

7.5.6 Ramp Selection

The resistor from RAMP to GND sets the ramp compensation level. See the Electrical Characteristics table for the resistor settings corresponding to each ramp level.

7.5.7 Active Phases

Normally, the controller is configured to operate in 3-phase mode. To enable 2-phase mode, tie the CSP3 pin to a 3.3-V supply and the CSN3 pin to GND. To enable 1-phase mode, tie the CSP2 and CSP3 pins to a 3.3-V supply and tie the CSN2 and CSN3 pins to GND.

7.6.1 Voltage Select Register (VSR) (00h)

• Type: Read and write
• Power-up value: 48h. This value can be changed before the rising edge of EN to change BOOT voltage.
• EN rising (after power-up): prior programmed value
• See Table 2 for exact values
• A command to set VSR < 19h (minimum VID) generates a NAK and the VSR remains at the prior value

7.6.2 IMON Register (03h)

• Type: Read only
• Power-up value: 00h
• EN rising (after power-up):00h

7.6.3 VMAX Register (04h)

• Type: Read / write (see below)
• Power-up value: 1.28 V (OTP value)
• EN rising (after power-up): Last written value

Bit definitions:

7.6.4 Power State Register (06h)

• Type: Read and write
• Power-up value: 00h
• EN rising (after power-up): 00h

Bit definitions:

7.6.5 SLEW Register (07h)

• Type: Read and write (see below)
• Power-up value: Defined by SLEWA pin at power-up
• EN rising (after power-up): Last written value
• Write only a single ‘1’ for the SLEW rate desired

7.6.6 Lot Code Registers (10-13h)

• Type: 8-bits; read only
• Power-up value: Programmed at factory

7.6.7 Fault Register (14h)

• Type: 8-bits; read only
• Power-up value: 00h