7.3.1 Controlling the Internal LED Bypass Switches

The TPS92661 device (LED Matrix Manager) consists of 12 series connected bypass switches between terminals LED12 and LED0. Each bypass switch, when driven to an off state, allows the string current to flow through the corresponding parallel-connected LED, turning the LED on. Conversely, driving the bypass switch to an on state shunts the current through the bypass switch and turns the LED off.

7.3.2 Internal Switch Resistance

Each single switch (connected between LED_n and LED_n–1) has a measurable typical R_DS(on) value of 225 mΩ. This measurement includes the actual on-resistance (R_DS(on)) of the switch and the resistance of the two internally connected bond wires. When multiple series switches are on, the effective resistance is not simply the number of channels multiplied by 225 mΩ because there are not two conducting bond wires for every series-connected switch. For this reason the all-switches on-resistance (R_ALL(on)) is specified in the Electrical Characteristics table. This value includes the twelve R_DS(on) on-resistances and the resistance of the bond wires at each end of the series connected switches.

The dominant power loss mechanism In the TPS92661 device, is I²R loss through the switches. Other power loss sources are always less than 50 mW. When calculating the power dissipation of the TPS92661 device switches, use Equation 1 for the best estimation of this power loss.

Equation 1.

where

• n is the number of channels

See the 6 LED, 1.5-A Application section for a sample calculation.

7.3.3 PWM Dimming

The TPS92661 device provides 10-bit PWM dimming of each individual LED. The LED turn-on and turn-off times are separately programmed for each LED. The LEDxON registers and LEDxOFF registers (where x = 1 to 12) determine the LED turn-on and turn-off times, respectively, within the PWM dimming period. Phase shifting can be accomplished by staggering the LEDxON times or LEDxOFF times. The 10-bit internal PWM Period Counter (TCNT) is compared against the LEDxON and LEDxOFF values.

When TCNT reaches the programmed LEDxON value for a given LED, the corresponding bypass switch is turned off to force current through the LED. Similarly, when TCNT reaches the programmed LEDxOFF value, the bypass switch is turned on to turn off the LED. TCNT counts continuously from 0 to 1023 and returns to 0 again. The LED PWM dimming period equals 1024 times the internally divided, programmable PWM clock period. Figure 9 shows an example of LED PWM using values of LEDxON = 250 and LEDxOFF = 800.

Figure 9. LED PWM Example

Because the LEDxON and LEDxOFF times are completely programmable, this allows the system flexibility to phase shift the leading edge (LED On), the trailing edge (LED Off), or double-edge PWM.

The comparison circuitry consists of a digital comparator, along with an AND gate to allow that particular comparison to propagate to the LED switch. The TCNT counter value is continuously compared against the value programmed into the LED On/Off registers. The ENON bit that corresponds to that particular LED determines whether or not that comparison has any effect at the LED. The logic is represented in Figure 10.

Figure 10. PWM Dimming Control Logic

7.3.4 PWM Clock

The PWM clock that drives TCNT is a divided-down version of the CLK input. The divider is programmed by writing to the PWM clock divider register (PCKDIV). The divider comprises two dividers in series: a power-of-2 clock divider followed by a decimal count divider (see Figure 11 and PWM Clock Divider Register (PCKDIV) for PCKDIV bitmap). Upon power-up, the PWM clock divider is programmed to a divisor value of 16.

Figure 11. PWM Clock Divider

7.3.5 PWM Synchronization

Upon power-up, the TCNT counter is reset to 0. The TCNT counter is clocked by the internal PWM clock. In order to correctly synchronize multiple TPS92661 devices on the same network, two conditions must be met:

• All TPS92661 devices must be clocked by the same clock on the CLK terminal.
• All TPS92661 devices must be programmed with the same PWM clock dividers (PCKDIV).

Assuming that these conditions are met, the TPS92661 devices may be synchronized by either of two methods:

1. As shown in Figure 12, the TPS92661 device includes a synchronization input/output (SYNC) and a synchronization master bit (SCMAST) in the system configuration register (SYSCFG). If SCMAST is set to 1, the TPS92661 device drives the SYNC terminal. The TPS92661 device generates a high pulse that is one-half of a PWM period on SYNC when TCNT and the PWM clock divider are about to roll over to 0. This SYNC signal can be fed to other TPS92661 devices. In other words, either the MCU can drive SYNC, or only one TPS92661 device should have SCMAST set to 1. The rest of the TPS92661 devices on the network must have SCMAST set to 0. If SCMAST is set to 0 (the default value), a low-to-high transition on SYNC at least one CLK cycle resets both TCNT and the PWM clock divider to 0 after internally synchronizing to the rising edge of CLK. SYNC is a feed-through signal that may be tied to the next TPS92661 device in order to synchronize multiple TPS92661 devices with respect to each other.

NOTE

In order to prevent bus contention, ensure that the network design includes only one synchronization master.

2. The TCNT counter and PWM clock divider can both be reset to 0 at any time by issuing a broadcast write synchronization command. Due to UART bit sampling variability, the synchronization is guaranteed to be within only 16 CLK cycles between TPS92661 devices.

Figure 12. PWM Synchronization

Figure 13 and Figure 14 show an example of two non-synchronized TPS92661 devices and two synchronized devices respectively. In this example all twelve channels on each device are programmed with LED_ON = 0 and LED_OFF = 128. In the non-synchronized example TCNT = 0 occurs at two different places in time. By using the SYNC function, TCNT = 0 occurs simultaneously for both devices.

CH1: (Dark Blue) Device 1 LED string voltage

CH2: (Light Blue) Device 2 LED string voltage

CH3: (Pink) SYNC signal as generated by 1 device

Figure 13. Non-Synchronized TPS92661 Devices

CH1: (Dark Blue) Device 1 LED string voltage

CH2: (Light Blue) Device 2 LED string voltage

CH3: (Pink) SYNC signal as generated by 1 device

Figure 14. Actively Synchronized TPS92661 Devices

7.3.6 Switch Slew Control

The gate drive control of each series switch slows the rate of change of current through the device. This control eases EMI requirements and aids in the system operation. The switching transition controls the current through the switch at each edge to approximately 800 mA/2 µs. The internal circuitry of the device controls the slew rate. The user cannot change the slew rate. The rise and fall slew rates are matched to ensure accurate representation of the PWM duty cycle. These slew rates assume no LED string capacitance.

Figure 15. TPS92661 Slew Rate Control

7.3.7 Effect of Phase Shifting LED Duty Cycles

Figure 16 and Figure 17 show the effective system input current (CH4, green trace) and V_(LED12-LED0) string voltage (CH1, blue trace) for various phase shift settings. The results illustrate the advantages of adjusting the phase shift value to minimize the variation in input current. Figure 16 illustrates a zero phase shift condition by setting all twelve LEDxON values to zero and all twelve LEDxOFF values to 128. Figure 17 illustrates optimal phase shifting where all twelve LEDxON values are spaced by a count of 85 (0, 85, 170, 235, ...). The input current variation is greatly reduced with optimal phase shifting as all twelve channels do not draw current from the input simultaneously. This reduces demands on the energy storage capacitance at the system input.

No Phase Shift

Duty Cycle = 128/1024

Figure 16. Single Channel,

Phase Shift = 85

Duty Cycle = 128/1024

Figure 17. Single Channel

7.3.8 LED Fault Detection and Protection

Each individual bypass switch is driven by a floating driver which is powered by the charge pump (see Functional Block Diagram). The steady floating driver supply also enables continuous protection and monitoring of LED open and short events.

In the event of an OPEN LED failure, an internal comparator monitors the drain-to-source voltage of the internal switch. If the voltage exceeds V_TH-O (typical 6 V) the device overrides the switch-off signal and turns on the switch. This action maintains current flow in the rest of the LED string in the presence of a faulty or damaged LED and protects the internal switch. The internal latch holds this state until a subsequent on and off cycle at which time the switch attempts to turn off again, and the condition is re-evaluated. The protection circuit also sets the corresponding bit in the FAULT register described in the Diagnostic Registerssection . The controller can poll this register to determine whether a fault has occurred.

When the device resets a FAULT bit in the register array by writing the bit back to zero, it then clears the latch and re-enables the OPEN switching transition of the corresponding LED. This feature allows the controller to perform multiple checks of the LED fault so that false LED faults can be filtered via software.

Similar to LED open detection, an LED short is detected via monitoring the drain-to-source voltage of the internal switch. If the voltage does not exceed the V_TH-S threshold by the end of the PWM cycle, the same fault register bit is set. Both short and open cases are handled by the same register as each case has the equivalent outcome, which is that the channel is bypassed. (see Figure 18)

Figure 18. Fault Detection Block

7.3.8.1 Fault Reporting and Timing

Fault detection and protection occur immediately and are independent of any internal clock. The device detects an overvoltage condition when the channel voltage rises to the OVP (overvoltage protection) comparator threshold. The channel switch is then latched ON with a delay of approximately 50 ns (typical). This detection generates a fault signal that is sent to the internal fault register when TCNT = LEDxOFF where it can be polled by the user. Similarly, the short detection fault signal is sent with the same timing. The Diagnostic Registers are updated in a maximum time of one full PWM period (a PWM count of 1024). Due to internal propagation delays the LED On-time count must conform to Equation 2 for accurate fault reporting. For typical applications this may require fault reporting to be ignored at duty cycles less than 1%.

Equation 2.

t₁ LEDxON = TCNT

t₂ Open detected

t₃ FAULT register updated

Figure 19. LED Open Fault Detect Timing

7.3.8.1.1 LED Open Fault Detect Timing Example

In an LED open event, 12 LEDs are being turned on sequentially, creating the staircase waveform as shown in Figure 20. At approximately time = 280 µs, LED6 is commanded to turn on but it is open. The TPS92661 device fault circuit immediately clamps the node by turning the channel switch ON. As the LEDs in the string are turned off, the previously open LED remains shorted for that cycle as the system has detected the fault and forced the switch to stay on. Other channels continue to operate normally.

Figure 20. LED Open Detection and Protection

7.3.9 Glitch-Free Operation

To help eliminate glitches in the LED current during register updates, the TPS92661 device implements the atomic multi-byte writes function and the synchronous updates function.

7.3.9.2 Synchronous Updates

Serial communications are asynchronous to the TCNT period. The device can write LEDxON and LEDxOFF with any value from 0x000 to 0x3FF at any time within the TCNT period. Consider a situation where there are no timing restrictions on updating the final registers. When the device receives a new LEDxOFF value while the corresponding LED is on and TCNT is already greater than the new LEDxOFF value, the LED remains on until it reaches the LEDxOFF value in the next TCNT period. This can appear as a glitch in LED light output.

To overcome this issue, the device writes a new value LEDxOFF and stores it in a temporary register. The device updates the final register only after TCNT reaches the next LEDxON register value. The converse is true for write commands to a particular LEDxON. In that case, the device updates the final register only after TCNT reaches the next LEDxOFF value. This sequence allows the device to update the LEDxOFF registers at the corresponding LED turn-on time and update the LEDxON registers at the corresponding LED turn-off time.

When LEDxON and LEDxOFF are both set to the same value, the device interprets the setting as an LED off condition. This is equivalent to clearing the ENON bit for that particular LED. The next time TCNT reaches the common LEDxON and LEDxOFF value, the device ignores LEDxON and the LED turns off (if it was on) and remains off until the device writes LEDxON and/or LEDxOFF and updates them with different value(s). More specifically, the LEDOFF comparison takes precedence over the LEDON comparison. Figure 21 illustrates an update example. Case (1) shows the resulting single PWM cycle on time that would occur if the writing of the registers were not handled through a temporary register. Case (2) shows the functionality of the TPS92661, where the register update is controlled, eliminating a false conduction cycle.

Figure 21. Glitch-Free LED Dimming Operation

7.3.10 Internal Oscillator and Watchdog Timers

The TPS92661 device includes two watchdog timers: a Clock Watchdog Timer and a Communications Watchdog Timer. The clock watchdog timer operates using a free-running internal oscillator. The communications watchdog timer operates using the incoming CLK signal. Both watchdog timers only operate when enabled after power-up by writing their respective enable bits to a 1 in the SYSCFG register (CKWEN for the clock watchdog timer and CMWEN for the communications watchdog timer). The Default LED State Register (DEFLED) determines which state the LEDs are placed in during a watchdog timeout period. (see the Default LED State Register (DEFLED) ) section for details.

The Figure 22 shows the subsequent state flow after a watchdog timer limit is reached.

Figure 22. Watchdog Timer Overflow Flow Chart

7.3.10.1 Clock Watchdog Timer

If the external CLK input stops toggling for 32 internal oscillator cycles ( approximately 14 µs, typical) the clock watchdog timer times out and all of the LEDs are turned on or off according to the programmed values in the DEFLED register. They remain in that state until CLK begins toggling again. During this time, the device does not receive or transmit UART communications. The device does not reset the internal registers in the event of clock loss, and the LEDs begin turning on and off according to their LEDxON/LEDxOFF register settings only when the clock returns. If the clock watchdog timer is not enabled the TPS92661 is capable of operating at frequencies down to 0 Hz.

Figure 23. Clock Watchdog Timer Logic

Figure 24. Communications Watchdog Timer Logic

7.4.1 Digital Interface Connections

7.4.2 Internal Pin-to-Pin Resistance

There are pin pairs for each digital I/O on the TPS92661 device. This allows for easy routing between multiple devices on a single sided PCB. To help estimate the voltage drop across the pin-to-pin connection, see Figure 26.

Figure 25. Pin-to-Pin Internal Resistance

Figure 26. Pin-to-Pin Cross-Device Resistance

7.4.3 UART Physical Layer

The microcontroller unit UART communicates with the TPS92661 device using serial TTL signaling. The TX and RX lines are connected to the TPS92661 device as shown in Figure 27. The pairs of TX and RX pins on the TPS92661 device are feed-through pins, and either pin may be used to connect the TPS92661 device to the network.

A tri-state buffer drives the TX output. In order to prevent false START bit detection by the microcontroller unit when a TPS92661 device releases the bus, place an external, 100-kΩ pull-up resistor on the RX input return line of the microcontroller unit.

Figure 27. Communications Connections

7.4.4 UART Clock and Baudrate

The UART operates with eight data bits, one stop bit and no parity (8 – 1). Figure 28 shows the waveform for an individual byte transfer on the TTL UART.

Figure 28. UART 8 – 1 Signaling

A logic “1” state occurs when the device drives the line to the VCC voltage. A logic “0” state occurs when the device drives the line to system ground. The line remains in the high/logic “1” state when idle. Figure 29 and Figure 30 illustrate sending actual data bytes and are intended to represent what an actual UART waveform displays on an oscilloscope or logic analyzer.

Figure 29. UART Sending 0x26 Byte (0010 0110)

Figure 30. UART Sending 0x26

The baud rate is based on the CLOCK input and is one-sixteenth of the CLOCK input frequency (see Table 1 for some examples). The UART uses 16× oversampling on the incoming asynchronous RX signal.

Set the master microcontroller unit to support the same baud rate as is defined by the input CLOCK frequency.

7.4.5 UART Communications Reset

The microcontroller unit can reset the device UART and protocol state machine at any time by holding the RX input low for a period of at least 12 bit times (16 × 12 CLK periods). This period signifies a break in communications and causes the TPS92661 devices on the network to reset to a known-good state for receiving the next command frame. The device immediately aborts any response frames in progress.

7.4.6 UART Device Addressing

Connecting terminals ADR2, ADR1, and ADR0 to GND or VCC sets the device address for each TPS92661 device. This allows up to eight different devices (addressable (0h to 7h)) for a total of 8 × 12 = 96 LEDs per array. See Table 2 for device address configuration.

7.4.7 UART Communications Protocol

The UART communication process uses a command/response protocol mastered by the MCU to write and read the registers on each TPS92661 device. This means that the TPS92661 device never initiates traffic onto the network. The protocol maps the registers into an address space on each device. All of the registers are read-write (R/W). See the Registers section for a register list.

The MCU uses the protocol to initiate a communication transaction by sending a command frame. This command frame addresses either one TPS92661 device directly or broadcasts to all TPS92661 devices on the network. This addressing may cause a response frame to be sent back from the slave TPS92661 device depending on the command type of the command frame. There are three types of command frames:

• Single Device Write from MCU to a specific TPS92661 device (1, 2, 5, 10 or 15 bytes of data)
• Single Device Read from MCU to a specific TPS92661 device (1, 2, 5, 10 or 15 bytes of data)
• Broadcast Write from the MCU to all TPS92661 devices (0, 1, 2, 5, 10 or 15 bytes of data)

There is only one response frame type. An addressed slave following a ‘Single Device Read’ command from the master MCU sends his frame type.

All command and response frames are multi-byte and the total number of transmitted bytes depends on the specific command type being communicated.

7.4.8 Transaction Frame Description

There are four byte-types used within a transaction frame. These include the following:

• Frame Initialization (1 byte)
• Register Address (1 byte)
• N Data Bytes (N = 0, 1, 2, 5, 10 or 15)
• Cyclic Redundancy Code (CRC) error checking (2 bytes)

7.4.9 Frame Initialization Byte

The frame initialization byte identifies the frame as being either a command frame or response frame. The command frame byte includes fields specifying the request type (which details the number of bytes to be sent) and the slave device ID. The response frame includes the number of bytes to be received by the microcontroller.

The fields shown in the frame initialization byte above are described in the table below.

7.4.10 Register Address

The protocol allows 1, 2, 5, 10 or 15 successive register locations from the addressed register to be written by a single command frame. The register address byte identifies the first TPS92661 device register being written or read, as described in the Register Map section.

7.4.11 Data Bytes

The frame initialization byte specifies the number of data bytes to be included in the frame.

7.4.12 CRC Bytes

CRC-16-IBM calculates the CRC bytes. The CRC bytes allow detection of errors within the transaction frame. The device increments the CRC Error Count Register (CERRCNT) each time a CRC error occurs (see Register Map for details).

7.4.13 Registers

The registers in the TPS92661 device contain programmed information and operating status. During the power-up period, the TPS92661 device resets the registers to the default values as listed below. Register addresses marked RESERVED or not shown in the register map may be written with any value but always returns a 0.

7.5.1 Read / Write Register Flow Chart

7.5.1.1 Register Write Flow Chart

Figure 31. Register Write Example

7.5.1.2 Register Read Flow Chart

Figure 32. Register Read Example

7.5.2 Complete Transaction Example

The pseudo-code below shows a pair of transactions: a write of the LEDOFF times for LEDs 1-4 followed by a read of the same registers (LED1OFF = 200, LED2OFF = 410, LED3OFF = 620, LED4OFF = 830).

As an additional example, the following pseudo-code shows a 2-byte write to TPS92661 Address 5, Register 0xB0 (ENON) with data of 0x55 to register 0xB0 and 0x05 to register 0xB1. Data sent (hex): 8D B0 55 05 D5 D8

The UART waveform associated with the example in Table 6 is shown in Figure 33.

Figure 33. 2-Byte Write Example Waveform

After this write had completed, the device enables all of the odd numbered LEDs (LED1, LED3, …, LED11) to turn on when TCNT = LEDxON register, while all of the even numbered LEDs remain off.

7.5.3 CRC Calculation Programming Examples

The C function below shows an example of how to generate the CRC bytes correctly for a transmission to the TPS92661 devices:

The CRC is transmitted LSByte first to/from the TPS92661 device.

Upon reading data from the TPS92661 device, the MCU should calculate and compare the CRC to determine whether valid data was received.

One way to perform the bit reversal is shown in the following C code:

7.5.4 Code Examples to Implement Register Reads/Writes

The C functions below show examples of how to code a single register write and single register read. It is recommended that the user get this code running first and then expand to some of the other commands and multi-byte reads and writes.

Write Example:

Read Example:

Table 7. Register Map