| These bits are set by the PHY when an unmasked
change occurs on the corresponding internal
signal. The PHY will automatically clear all bits
when the Link reads this register, or when Low
Power Mode is entered. The PHY also clears this
register when Serial Mode or Carkit Mode is
entered regardless of the value of ClockSuspendM.
The PHY follows the rules defined in Table 26 of
the ULPI spec for setting any latch register bit.
It is important to note that if register read data
is returned to the Link in the same cycle that a
USB Interrupt Latch bit is to be set, the
interrupt condition is given immediately in the
register read data and the Latch bit is not
set. Note that it is optional for the Link to read the
USB Interrupt Latch register in Synchronous Mode
because the RX CMD byte already indicates the
interrupt source directly |