ZHCSM73 September 2021 TUSB217A-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP (1) | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER | ||||||
| IACTIVE_HS | High Speed Active Current | USB channel = HS mode. 480 Mbps traffic. VCC supply stable, with Boost = Max | 22 | 36 | mA | |
| IIDLE_HS | High Speed Idle Current | USB channel = HS mode, no traffic. VCC supply stable, Boost = Max | 22 | 36 | mA | |
| IHS_SUPSPEND | High Speed Suspend Current | USB channel = HS Suspend mode. VCC supply stable | 0.75 | 1.4 | mA | |
| IFS | Full-Speed Current | USB channel = FS mode, 12 Mbps traffic, Vcc supply stable | 0.75 | 1.4 | mA | |
| IDISCONN | Disconnect Power | Host side application. No device attachment. | 0.80 | 1.4 | mA | |
| ISHUTDN | Shutdown Power | RSTN driven low, VCC supply stable | 60 | 115 | μA | |
| CONTROL PIN LEAKAGE | ||||||
| ILKG_FS | Pin failsafe leakage current for SDA, RSTN | VCC = 0 V, pin at VIH, max | 10 | 15 | μA | |
| ILKG_FS | Pin failsafe leakage current for RX_SEN | VCC = 0 V, pin at VIH, max | 6 | 15 | μA | |
| ILKG_FS | Pin failsafe leakage current for SCL | VCC = 0 V, pin at VIH, max | 70 | nA | ||
| INPUT RSTN | ||||||
| VIH | High level input voltage | 1.5 | 3.6 | V | ||
| VIL | Low-level input voltage | 0 | 0.5 | V | ||
| IIH | High level input current | VIH = 3.6 V, RPU enabled | ±15 | μA | ||
| IIL | Low level input current | VIL = 0V, RPU enabled | ±20 | μA | ||
| INPUT DIGITAL | ||||||
| VIH | High level input voltage (DCP/CDP) | 1.5 | 3.6 | V | ||
| VIL | Low-level input voltage (DCP/CDP) | 0 | 0.5 | V | ||
| IIL | Low level input current | VIL = 0V | ±20 | μA | ||
| IIH | High level input current | VIH = 3.6 V | ±15 | μA | ||
| INPUT RX_SEN (3-level input, for mid level leave pin floating) | ||||||
| VIH(Max) | Maximum High level input voltage |
VCC = 2.3V to 6.5V | 5.0 | V | ||
| VIH(Min) | Minimum High level input voltage |
VCC > 4.5V | 3.3 | V | ||
| VCC = 2.3V to 4.5V (% of VCC) | 75 | % | ||||
| VIL | Low level input voltage |
VCC > 4.5V | 0.75 | V | ||
| VCC = 2.3V to 4.5V (% of VCC) | 15 | % | ||||
| INPUT BOOST | ||||||
| RBOOST_LVL0 | External pulldown resistor for BOOST Level 0 | 160 | Ω | |||
| RBOOST_LVL1 | External pulldown resistor for BOOST Level 1 | 1.5 | 1.8 | 2 | kΩ | |
| RBOOST_LVL2 | External pulldown resistor for BOOST Level 2 | 3.4 | 3.6 | 3.96 | kΩ | |
| RBOOST_LVL3 | External pulldown resistor for BOOST Level 3 to remove upper limit for resistor value, can be left open | 7.5 | kΩ | |||
| OUTPUTS CD, ENA_HS | ||||||
| VOH | High level output voltage for CD and ENA_HS | IO = –50 μA, VCC >= 3.0V | 2.5 | V | ||
| VOH | High level output voltage for CD | IO = –25 μA, VCC = 2.3V | 1.7 | V | ||
| VOH | High level output voltage for ENA_HS | IO = –25 μA, VCC = 2.3V | 1.8 | V | ||
| VOL | Low level output voltage for CD and ENA_HS | IO = 50 μA | 0.3 | V | ||
| I2C | ||||||
| CI2C_BUS | I2C Bus Capacitance | 4 | 150 | pF | ||
| IOL | I2C open drain output current | VOL = 0.4V | 1.5 | mA | ||
| VIL | 2.3V<= VCC<= 4.3V, VI2C_BUS = 1.8V +/-10% | RPull-up =1.6k? to 2.5k?, % of VI2C_BUS | 25 | % | ||
| VIL | VI2C_BUS = 3.3V +/-10% | RPull-up =2.8k? to 7k?, % of VI2C_BUS | 25 | % | ||
| VIH | 2.3V<= VCC<= 4.3V, VI2C_BUS = 1.8V +/-10% | RPull-up =1.6k? to 2.5k?, % of VI2C_BUS | 80 | % | ||
| VIH | VI2C_BUS = 3.3V +/-10% | RPull-up =2.8k? to 7k?, % of VI2C_BUS | 75 | % | ||
| RPull-up | VI2C_BUS = 1.8V +/-10% | 1.6 | 2 | 2.5 | k? | |
| RPull-up | VI2C_BUS = 3.3V +/-10% | 2.8 | 4.7 | 7 | k? | |
| SCL Frequency | 100 | kHz | ||||
| DxP, DxM | ||||||
| CIO_DXX | Capacitance to GND | Measured with VNA at 240 MHz, VCC supply stable, Redriver off | 2.5 | pF | ||