9.2.2.1 Switching Frequency

The choice of switching frequency is generally somewhat arbitrary. The switching frequency must be high enough to make the power circuits small and minimize the distortion and must be low enough to keep the efficiency high. In most applications a switching frequency in the range of 20 kHz to 300 kHz proves to be an acceptable compromise. The example converter uses a switching frequency of 100 kHz as a compromise between size and efficiency. The value of the inductor will be reasonably small and cusp distortion will be minimized, the inductor will be physically small and the loss due to the output diode will not be excessive. Converters operating at higher power levels may find that a lower switching frequency is desirable to minimize the power losses. Turn-on snubbers for the switch will reduce the switching losses and can be very effective in allowing a converter to operate at high switching frequency with very-high efficiency.

9.2.2.2 Inductor Selection

The inductor determines the amount of high frequency ripple current in the input and its value is chosen to give some specific value of ripple current. Inductor value selection begins with the peak current of the input sinusoid. The maximum peak current occurs at the peak of the minimum line voltage and is given by:

Equation 3.

For the example converter the maximum peak line current is 4.42 A at a V_in of 80Vac.

The maximum ripple current in a boost converter occurs when the duty factor is 50% which is also when the boost ratio M = V_o / V_in = 2. The peak value of inductor current generally does not occur at this point since the peak value is determined by the peak value of the programmed sinusoid. The peak value of inductor ripple current is important for calculating the required attenuation of the input filter. Figure 12 is a graph of the peak-to-peak ripple current in the inductor versus input voltage for the example converter.

The peak-to-peak ripple current in the inductor is normally chosen to be about 20% of the maximum peak line current. This is a somewhat arbitrary decision since this is usually not the maximum value of the high frequency ripple current. A larger value of ripple current will put the converter into the discontinuous conduction mode for a larger portion of the rectified line current cycle and means that the input filter must be larger to attenuate more high frequency ripple current. The UC3854, with average current mode control, allows the boost stage to move between continuous and discontinuous modes of operation without a performance change.

The value of the inductor is selected from the peak current at the top of the half sine wave at low input voltage, the duty factor D at that input voltage and the switching frequency. The two equations necessary are given below:

Equation 4.

Equation 5.

where

• ΔI is the peak-to-peak ripple current.
• In the example 250-W converter:
  • D = 0.71
  • Δl = 900 mA
  • L = 0.89 mH
• For convenience, the value of L is rounded up to 1.0 mH.

The high-frequency ripple current is added to the line current peak so the peak inductor current is the sum of peak line current and half of the peak-to-peak high frequency ripple current. The inductor must be designed to handle this current level. For our example the peak inductor current is 5.0 A. The peak current limit will be set about 10% higher at 5.5 A.

9.2.2.3 Output Capacitor

The factors involved in the selection of the output capacitor are the switching frequency ripple current, the second harmonic ripple current, the DC output voltage, the output ripple voltage and the hold-up time. The total current through the output capacitor is the RMS value of the switching frequency ripple current and the second harmonic of the line current. The large electrolytic capacitors which are normally chosen for the output capacitor have an equivalent series resistance which changes with frequency and is generally high at low frequencies. The amount of current which the capacitor can handle is generally determined by the temperature rise. It is usually not necessary to calculate an exact value for the temperature rise. It is usually adequate to calculate the temperature rise due to the high frequency ripple current and the low frequency ripple current and add them together. The capacitor data sheet will provide the necessary ESR and temperature rise information.

The hold-up time of the output often dominates any other consideration in output capacitor selection. Hold-up is the length of time that the output voltage remains within a specified range after input power has been turned off. Hold-up times of 15 to 50 ms are typical. In off-line power supplies with a 400 Vdc output the hold-up requirement generally works out to between 1 and 2 pF/W of output. In our 250-W example, the output capacitor is 450 pF. If hold-up is not required the capacitor will be much smaller, perhaps 0.2 pF/W, and then ripple current and ripple voltage are the major concern.

Hold-up time is a function of the amount of energy stored in the output capacitor, the load power, output voltage and the minimum voltage the load will operate at. This can be expressed in an equation to define the capacitance value in terms of the holdup time.

Equation 6.

where

• C_O is the output capacitor.
• P_out is the load power.
• Δt is the hold-up time
• V_o is the output voltage.
• V_o(min) is the minimum voltage the load will operate at.
• For the example converter:
  • P_out is 250 W.
  • Δt is 64 ms.
  • V_O is 400 V.
  • V_O(min) is 300 V.
  • So, C_o is 450 µF.

9.2.2.4 Switch and Diode

The switch and diode must have ratings which are sufficient to ensure reliable operation. The switch must have a current rating at least equal to the maximum peak current in the inductor and a voltage rating at least equal to the output voltage. The same is true for the output diode. The output diode must also be very fast to reduce the switch turn-on power dissipation and to keep its own losses low. The switch and diode must have some level of derating and this will vary depending on the application.

Figure 10. Current Transformers Used With Negative Output

Figure 11. Current Transformers Used With Positive Output

For the example circuit the diode is a high speed, high voltage type with 35-ns reverse recovery, 600 Vdc breakdown, and 8-A forward current ratings. The power MOSFET in the example circuit has a 500 Vdc breakdown and 23 Adc current rating. A major portion of the losses in the switch are due to the turn-off current in the diode. The peak power dissipation in the switch is high since it must carry full load current plus the diode reverse recovery current at full output voltage from the time it turns on until the diode turns off. The diode in the example circuit was chosen for its fast turn off and the switch was oversized to handle the high peak power dissipation. A turn on snubber for the switch would have allowed a smaller switch and a slightly slower diode.

9.2.2.5 Current Sensing

There are two general methods for current sensing, a sense resistor in the ground return of the converter or two current transformers. The sense resistor is the least expensive method and is most appropriate at low power or current levels. The power dissipation in the resistor may become quite large at higher current levels and in that case the current transformers are more appropriate. Two current transformers are required, one for the switch current and one for the diode current, to produce an analog of the inductor current as is required for average current mode control. The current transformers must operate over a very-wide duty factor range and this can be difficult to achieve without saturating them. Current transformer operation is outside the scope of this paper but Unitrode has Design Note DN-41 which discusses the problem in some detail.

The current transformers may be configured for either a positive output voltage or a negative output voltage. In the negative output configuration, shown in Figure 10, the peak current limit on pin 2 of the UC3854 is easy to implement. In the positive output configuration, shown in Figure 11, this feature may be lost. It can be added back by putting another resistor in series with the ground leg of the current transformer which senses the switch current.

The configuration of the multiplier output and the current error amplifier are different depending on whether a resistor is used for current sensing or whether current transformers with positive output voltages are used for current sensing. Both work equally well and the configurations of the current error amplifier are shown in Figure 10 and Figure 11, respectively. The positive output current transformer configuration requires the inverting input to the integrator be connected to the sense resistor and the resistor at the output of the multiplier be connected to ground. (see Figure 11) The voltage at the output of the multiplier is not zero but is the programming voltage for the current loop and it will have the half sine wave shape which is necessary for the current loop.

The resistor current sense configuration is used in the example converter (Figure 9) so the inverting input to the current error amplifier (pin 4) is connected to ground through R_ci. The current error amplifier is configured as an integrator at low frequencies for average current mode control so the average voltage at the non-inverting input of the current error amplifier (pin 5, which it shares with the multiplier output) must be 0. The non-inverting input to the current error amplifier acts like a summing junction for the current control loop and adds the multiplier output current to the current from the sense resistor (which flows through the programming resistor R_mo). The difference controls the boost regulator. The voltage at the inverting input of the current error amplifier (pin 4) will be small at low frequencies because the gain at low frequencies is large. The gain at high frequencies is small so relatively large voltages at the switching frequency may be present. But, the average voltage on pin 4 must be 0 because it is connected through R_ci to ground.

The voltage across R_s, the current sense resistor in the example converter, goes negative with respect to ground so it is important to be sure that the pins of the UC3854 do not go below ground. The voltage across the sense resistor should be kept small and pins 2 and 5 should be clamped to prevent their going negative. A peak value of 1 V or so across the sense resistor provides a signal large enough to have good noise margin but which is small enough to have low power dissipation. There is a great deal of flexibility in choosing the value of the sense resistor. A 0.25-Ω resistor was chosen for R_s in the example converter and at the worst case peak current of 5.6 A gives a maximum voltage of 1.40-V peak.

9.2.2.6 Peak Current Limit

The peak current limit on the UC3854 turns the switch off when the instantaneous current through it exceeds the maximum value and is activated when pin 2 is pulled below ground. The current limit value is set by a simple voltage divider from the reference voltage to the current sense resistor. The equation for the voltage divider is given as follows:

Equation 7.

where

• R_pk1 and R_pk2 are the resistors of the voltage divider.
• V_ref is 7.5 V on the UC3854.
• V_rs is the voltage across the sense resistor R_s at the current limit point.

The current through R_pk2 should be around 1 mA. The peak current limit in the example circuit is set at 5.4 A with an R_pk1 of 10 kΩ and R_pk2 of 1.8 kΩ. A small capacitor, C_pk, has been added to give extra noise immunity when operating at low line and this also increases the current limit slightly.

9.2.2.7 Multiplier Set-up

The multiplier/divider is the heart of the power factor corrector. The output of the multiplier programs the current loop to control the input current to give a high power factor. The output of the multiplier is therefore a signal which represents the input line current.

Unlike most design tasks where the design begins at the output and proceeds to the input the design of the multiplier circuits must begin with the inputs. There are three inputs to the multiplier circuits: the programming current l_ac (pin 6) the feedforward voltage V_ff from the input (pin 8) and the voltage error amplifier output voltage V_vea (pin 7). The multiplier output current is Imo (pin 5) and it is related to the three inputs by the following equation:

Equation 8.

where

• Km is a constant in the multiplier and is equal to 1.0
• lac is the programming current from the rectified input voltage
• Vvea is the output of the voltage error amplifier
• Vff is the feedforward voltage.

9.2.2.8 Feedforward Voltage

V_ff is the input to the squaring circuit and the UC3854 squaring circuit generally operates with a V_ff range of 1.4 to 4.5 V. The UC3854 has an internal clamp which limits the effective value of V_ff to 4.5 V even if the input goes above that value. The voltage divider for the V_ff input has three resistors (R_ff1, R_ff2, and R_ff3 – see Figure 9) and two capacitors (C_ff1 and C_ff2) and so it filters as well as providing two outputs. The resistors and capacitors of the divider form a second order low pass filter so the DC output is proportional to the average value of the input half sine wave. The average value is 90% of the RMS value of a half sine wave. If the RMS value of the AC input voltage is 270 Vac the average value of a half sine will be 243 Vdc and the peak will be 382 V.

The V_ff voltage divider has two DC conditions to meet. At high- input line voltage V_ff should not be greater than 4.5 V. At this voltage the V_ff input clamps so the feedforward function is lost. The voltage divider should be set up so that V_ff is equal to 1.414 V when V_in is at its low line value and the upper node of the voltage divider, V_ffc, should be about 7.5 V. This allows V_ff to be clamped as described in Unitrode Design Note DN-39B. There is an internal current limit which holds the multiplier output constant if the V_ff input goes below 1.414 V. The V_ff input should always be set up so that V_ff is equal to 1.414 V at the minimum input voltage. This may cause V_ff to clip on the high end of the input voltage range if there is an extremely wide AC line voltage input range. However, it is preferable to have V_ff clip at the high end rather than to have the multiplier output clip on the low end of the range. If V_ff clips the voltage loop gain will change but the effect on the overall system will be small whereas the multiplier clipping will cause large amounts of distortion in the input current waveform.

The example circuit uses the UC3854 so the maximum value of V_ff is 4.5 V. If R_ff1, the top resistor of the divider, is 910 kΩ and R_ff2, the middle resistor, is 91 kΩ and R_ff3, the bottom resistor, is 20 kΩ the maximum value of V_ff will be 4.76 V when the input voltage is 270 Vac RMS and the DC average value will be 243 V. When the input voltage is 80 Vac RMS the average value is 72 V and V_ff is 1.41 Vdc. Also at V_in = 80 Vac the voltage at the upper node on the voltage divider, V_ffc, will be 7.83 V. Note that the high end of the range goes above 4.5 V so that the low end of the range will not go below 1.41 V.

The output of the voltage error amplifier is the next piece of the multiplier setup. The output of the voltage error amplifier, V_vea, is clamped inside the UC3854 at 5.6 V. The output of the voltage error amplifier corresponds to the input power of the converter. The feedforward voltage causes the power input to remain constant at given V_vea voltage regardless of line voltage changes. If 5.0 V is established as the maximum normal operating level then 5.6 V gives an overload power limit which is 12% higher.

The clamp on the output of the voltage error amplifier is what sets the minimum value of V_ff at 1.414 V. This can be seen by plugging these values into the equation for the multiplier output current given above. When V_ff is large the inherent errors of the multiplier are magnified because V_vea/V_ff becomes small. If the application has a wide input voltage range and if a very-low harmonic distortion is required then V_ff may be changed to the range of 0.7 to 3.5 V. To do this an external clamp must be added to the voltage error amplifier to hold its output below 2.00 V. In general, however, this is not a recommended practice.

9.2.2.9 Multiplier Input Current

The operating current for the multiplier comes from the input voltage through R_vac. The multiplier has the best linearity at relatively high currents, but the recommended maximum current is 0.6 mA. At high line the peak voltage for the example circuit is 382 Vdc and the voltage on pin 6 of the UC3854 is 6.0 Vdc. A 620 kΩ value for R_vac will give an lac of 0.6-mA maximum. For proper operation near the cusp of the input waveform when V_in = 0 a bias current is needed because pin 6 is at 6.0 Vdc. A resistor, R_b1, is connected from V_ref to pin 6 to provide the small amount of bias current needed. R_b1 is equal to R_vac / 4. In the example circuit, a value of 150 kΩ for R_b1 will provide the correct bias.

The maximum output of the multiplier occurs at the peak of the input sine wave at low line. The maximum output current from the multiplier can be calculated from the equation for I_mo, given above, for this condition. The peak value of l_ac will be 182 µA when V_in is at low line. V_vea will be 5.0 V and V_ff will be 2.0. Imo will then be 365 µA maximum. I_mo may not be greater than twice lac so this represents the maximum current available at this input voltage and the peak input current to the power factor corrector will be limited accordingly.

The l_set current places another limitation on the multiplier output current. I_mo may not be larger than 3.75 / R_set. For the example circuit this gives R_set = 10.27 kΩ maximum so a value of 10 kΩ is chosen.

The current out of the multiplier, Imo, must be summed with a current proportional to the inductor current to close the voltage feedback loop. R_mo, a resistor from the output of the multiplier to the current sense resistor, performs the function and the multiplier output pin becomes the summing junction. The average voltage on pin 5 will be 0 under normal operation but there will be switching frequency ripple voltage which is amplitude modulated at twice the line frequency. The peak current in the boost inductor is to be limited to 5.6 A in the example circuit and the current sense resistor is 0.25 Ω so the peak voltage across the sense resistor is 1.4 V. The maximum multiplier output current is 365 µA so the summing resistor, R_mo, must be 3.84 kΩ and a 3.9-kΩ resistor is chosen.

9.2.2.10 Oscillator Frequency

The oscillator charging current is l_set and is determined by the value of R_set and the oscillator frequency is set by the timing capacitor and the charging current. The timing capacitor is determined from:

Equation 9.

where

• C_t is the value of the timing capacitor
• f_s is the switching frequency in Hertz.

For the example converter:

• f_s is 100 kHz and R_set is 10K so C_t is 0.00125 pF.

9.2.2.11 Current Error Amplifier Compensation

The current loop must be compensated for stable operation. The boost converter control to input current transfer function has a single pole response at high frequencies which is due to the impedance of the boost inductor and the sense resistor (R_s) forming a low pass filter. The equation for the control to input current transfer function is:

Equation 10.

where

• V_rs is the voltage across the input current sense resistor
• V_cea is the output of the current error amplifier.
• V_out is the DC output voltage
• V_s is the peak-to-peak amplitude of the oscillator ramp
• s_L is the impedance of the boost inductor (also jwL)
• R_s is the sense resistor (with a current transformer it will be R_s / N)

This equation is only valid for the region of interest between the resonant frequency of the filter (LC_o) and the switching frequency. Below resonance the output capacitor dominates and the equation is different.

The compensation of the current error amplifier provides flat gain near the switching frequency and uses the natural roll off of the boost power stage to give the correct compensation for the total loop. A zero at low frequency in the amplifier response gives the high gain which makes average current mode control work. The gain of the error amplifier near the switching frequency is determined by matching the down slope of the inductor current when the switch is off with the slope of the ramp generated by the oscillator. These two signals are the inputs of the PWM comparator in the UC3854.

The downslope of the inductor current has the units of amps per second and has a maximum value when the input voltage is zero. In other words, when the voltage differential between the input and output of the boost converter is greatest. At this point (V_in = 0) the inductor current is given by the ratio of the converter output voltage and the inductance (V_o / L). This current flows through the current sense resistor R_s and produces a voltage with the slope V_oR_s / L (with current sense transformers it will be V_oR_s/NL). This slope, multiplied by the gain of the current error amplifier at the switching frequency, must be equal to the slope of the oscillator ramp (also in volts per second) for proper compensation of the current loop. If the gain is too high the slope of the inductor current will be greater than the ramp and the loop can go unstable. The instability will occur near the cusp of the input waveform and will disappear as the input voltage increases.

The loop crossover frequency can be found from the above equation if the gain of the current error amplifier is multiplied with it and it is set equal to one. Then rearrange the equation and solve for the crossover frequency. The equation becomes:

Equation 11.

where

• ƒ_ci is the current loop crossover frequency
• R_cz / R_ci is the gain of the current error amplifier.

This procedure will give the best possible response for the current loop.

In the example converter the output voltage is 400 Vdc and the inductor is 1.0mH so the down slope of inductor current is 400 mA/µs. The current sense resistor is 0.25 Ω so the input to the current error amplifier is 100 mV/µs. The oscillator ramp of the UC3854 has a peak to peak value of 5.2 V and the switching frequency is 100 kHz so the ramp has a slope of 0.52 V/µs. The current error amplifier must have a gain of 5.2 at the switching frequency to make the slopes equal. With an input resistor (R_ci) value of 3.9K the feedback resistance (R_cz) is 20K to give the amplifier a gain of 5.2. The current loop crossover frequency is 15.9 kHz.

The placement of the zero in the current error amplifier response must be at or below the crossover frequency. If it is at the crossover frequency the phase margin will be 45°. If the zero is lower in frequency the phase margin will be greater. A 45° phase margin is very stable, has low overshoot and has good tolerance for component variations. The zero must be placed at the crossover frequency so the impedance of the capacitor at that frequency must be equal to the value of R_cz. The equation is: C_cz = 1 / (271 × ƒ_ci × R_cz). The example converter has R_cz = 20K and ƒ_ci = l5.9 kHz so C_cz = 500 pF. A value of 620 pF was chosen to give a little more phase margin.

A pole is normally added to the current error amplifier response near the switching frequency to reduce noise sensitivity. If the pole is above half the switching frequency the pole will not affect the frequency response of the control loop. The example converter uses a 62-pF capacitor for C_cp which gives a pole at 128 kHz. This is actually above the switching frequency so a larger value of capacitor could have been used but 62 pF is adequate in this case.

9.2.2.12 Voltage Error Amplifier Compensation

The voltage control loop must be compensated for stability but because the bandwidth of the voltage loop is so small compared to the switching frequency the requirements for the voltage control loop are really driven by the need to keep the input distortion to a minimum rather than by stability. The loop bandwidth must be low enough to attenuate the second harmonic of the line frequency on the output capacitor to keep the modulation of the input current small. The voltage error amplifier must also have enough phase shift so that what modulation remains will be in phase with the input line to keep the power factor high.

The basic low frequency model of the output stage is a current source driving a capacitor. The power stage and the current feedback loop compose the current source and the capacitor is the output capacitor. This forms an integrator and it has a gain characteristic which rolls off at a constant 20 dB per decade rate with increasing frequency. If the voltage feedback loop is closed around this it will be stable with constant gain in the voltage error amplifier. This is the technique which is used to stabilize the voltage loop. However, its performance at reducing distortion due to the second harmonic output ripple is miserable. A pole in the amplifier response is needed to reduce the amplitude of the ripple voltage and to shift the phase by 90°. The distortion criteria is used to define the gain of the voltage error amplifier at the second harmonic of the line frequency and then the unity gain crossover frequency is found and is used to determine the pole location in the voltage error amplifier frequency response.

The first step in designing the voltage error amplifier compensation is to determine the amount of ripple voltage present on the output capacitor. The peak value of the second harmonic voltage is given by:

Equation 12.

where

• V_opk is the peak value of the output ripple voltage (the peak to peak value will be twice this)
• ƒ_r is the ripple frequency which is the second harmonic of the input line frequency
• C_o is the value of the output capacitance and V_O is the DC output voltage.

The example converter has a peak ripple voltage of 1.84 Vpk. The amount of distortion which the ripple contributes to the input must be decided next. This decision is based on the specification for the converter. The example converter is specified for 3% THD so 0.75% THD is allocated to this component. This means that the ripple voltage at the output of the voltage error amplifier is limited to 1.5%. The voltage error amplifier has an effective output range (ΔV_vea) of 1.0 to 5.0 V so the peak ripple voltage at the output of the voltage error amplifier is give by V_vea(pk) = %Ripple × ΔV_vea. The example converter has a peak ripple voltage at the output of the voltage error amplifier of 60mVpk.

The gain of the voltage error amplifier, G_va, at the second harmonic ripple frequency is the ratio of the two values given above. The peak ripple voltage allowed on the output of the voltage error amplifier is divided by the peak ripple voltage on the output capacitor. For the example converter G_va is 0.0326.

The criteria for the choice of R_vi, the next step in the design process, are reasonably vague. The value must be low enough so that the operational amplifier bias currents will not have a large effect on the output and it must be high enough so that the power dissipation is small. In the example converter a 511-kΩ resistor was chosen for R_vi and it will have power dissipation of about 300 mW.

C_vf, the feedback capacitor sets the gain at the second harmonic ripple frequency and is chosen to give the voltage error amplifier the correct gain at the second harmonic of the line frequency. The equation is simply:

Equation 13.

The example converter has a C_vf value of 0.08 µF. If this value is rounded down to C_vf = 0.O47pF the phase margin will be a little better with only a little more distortion so this value was chosen.

The output voltage is set by the voltage divider R_vi and R_vd. The value of R_vi is already determined so R_vd is found from the desired output voltage and the reference voltage which is 7.50Vdc. In the example R_vd = 10 kΩ will give an output voltage of 390 Vdc. This could be trimmed up to 400VDC with a 414-kΩ resistor in parallel with Rvd but for this application 390 Vdc is acceptable. R_vd has no effect on the AC performance of the active power factor corrector. Its only effect is to set the DC output voltage.

The frequency of the pole in the voltage error amplifier can be found from setting the gain of the loop equation equal to one and solving for the frequency. The voltage loop gain is the product of the error amplifier gain and the boost stage gain, which can be expressed in terms of the input power. The multiplier, divider and squarer terms can all be lumped into the power stage gain and their effect is to transform the output of the voltage error amplifier into a power control signal as was noted earlier. This allows us to express the transfer function of the boost stage simply in terms of power. The equation is:

Equation 14.

where

• G_bst is the gain of the boost stage including the multiplier, divider and squarer
• P_in is the average input power
• X_CO is the impedance of the output capacitor
• ΔV_vea is the range of the voltage error amplifier output voltage (4 V on the UC3854)
• V_O is the DC output voltage.

The gain of the error amplifier above the pole in its frequency response is given by:

Equation 15.

where

• G_va is the gain of the voltage error amplifier
• X_cf is the impedance of the feedback capacitance
• R_vi is the input resistance.

The gain of the total voltage loop is the product of G_bst and G_va and is given by the this equation:

Equation 16.

Note that there are two terms which are dependent on f, X_co, and X_cf. This function has a second order slope (–40 dB per decade) so it must be a function of frequency squared. To solve for the unity gain frequency set G_v equal to one and rearrange the equation to solve for ƒ_vi. X_co is replaced with 1 / (2πƒ_r × R_vi × G_va) and X_cf is replaced with 1 / (2πƒ_rC_vf).

The equation becomes:

Equation 17.

Solving for ƒ_vi in the example converter gives ƒ_vi = 19.14 Hz. The value of R_vf can now be found by setting it equal to the impedance of C_vf at ƒ_vi. The equation is: R_vf = 1 l(2πƒ_viC_vf).

In the example converter a value of 177K is calculated and 174K is used.

9.2.2.13 Feedforward Voltage Divider Filter Capacitors

The percentage of second harmonic ripple voltage on the feedforward input to the multiplier results in the same percentage of third harmonic ripple current on the AC line. The capacitors in the feedforward voltage divider (C_ff1 and C_ff2) attenuate the ripple voltage from the rectified input voltage. The second harmonic ripple is 66.2% of the input AC line voltage. The amount of attenuation required, or the gain of the filter, is simply the amount of third harmonic distortion allocated to this distortion source divided by 66.2% which is the input to the divider. The example circuit has an allocation of 1.5% total harmonic distortion from this input so the required attenuation is G_ff = 1.5 / 66.2 = 0.0227.

The recommended divider string implements a second order filter because this gives a much faster response to changes in the RMS line voltage. Typically, it is about six times faster. The two poles of the filter are placed at the same frequency for the widest bandwidth. The total gain of the filter is the product of the gain of the two filter section so the gain of each section is the square root of the total gain. The two sections of the filter do not interact much because the impedances are different so they can be treated separately. In the example converter the gain of each filter section at the second harmonic frequency is 0.0227 or 0.15 for each section. This same relationship holds for the cutoff frequency which is needed to find the capacitor values. These are simple real poles so the cutoff frequency is the section gain times the ripple frequency or:

Equation 18.

The example converter has a filter gain of 0.0227 and a section gain of 0.15 and a ripple frequency of 120 Hz so the cutoff frequency is ƒ_c = 0.15 × 120 = 18 Hz.

The cutoff frequency is used to calculate the values for the filter capacitors since, in this application, the impedance of the capacitor will equal the impedance of the load resistance at the cutoff frequency. The two equations given below are used to calculate the two capacitor values.

Equation 19.

Equation 20.

In the example converter R_ff2 is 91 kΩ and R_ff3 is 20 kΩ; so,

so choose C_ff2 = 0.47 µF

This completes the design of the major circuits of an active power factor corrector.

9.2.2.14 Design Procedure Summary

This section contains a brief, step-by-step summary of the design procedure for an active power factor corrector. The example circuit used above is repeated here.

1. Specifications: Determine the operating requirements for the active power factor corrector.

Example:

• Pout (max): 250 W
• Vin range: 80 to 270 Vac
• Line frequency range: 47 to 65 Hz
• Output voltage: 400 Vdc
2. Select switching frequency:

Example: 100 kHz

3. Inductor selection:
   1. Maximum peak line current. P_in = P_out(max)
   Equation 23.

   Example: I_pk = 1.41 × 250 / 80 = 4.42 A

   2. Ripple current.
   Equation 24. ΔI = 0.2 × I_pk

   Example: ΔI = 0.2 × 4.42 = 0.2 × 4.42 = 0.9 A peak-to-peak

   3. Determine the duty factor at I_pk where V_in(peak) is the peak of the rectified line voltage at low line.
   Equation 25.

   Example: D = (400 – 113) / 400 = 0.71

   4. Calculate the inductance. ƒ_S is the switching frequency.
   Equation 26.

   Example:

   L = (1113 × 0.71) / (100000 × 0.9) = 0.89 mH

   Round up to 1.0 mH.

4. Select output capacitor. With hold-up time, use the equation below. Typical values for C_o are 1 µF to 2 µF per watt. If hold-up is not required use the second harmonic ripple voltage and total capacitor power dissipation to determine minimum size of the capacitor. At is the hold-up time in seconds and V₁ is the minimum output capacitor voltage.
Equation 27.

Example:

Equation 28. C_O = (2 × 250 × 34 µs) / (400 – 350) = 450 µF
5. Select current sensing resistor. If current transformers are used then include the turns ratio and decide whether the output will be positive or negative relative to circuit common. Keep the peak voltage across the resistor low. 1.0 V is a typical value for V_rs.
   1. Find
   Equation 29. T_lpk(max) = I_pk + ΔI / 2

   Example: l_pk(max) = 4.42 + 0.45 ≈ 5.0 A peak

   2. Calculate sense resistor value.
   Equation 30.

   Example: R_S = 1.0 / 5.0 = 0.20 Ω. Choose 0.25 Ω

   3. Calculate the actual peak sense voltage. V_rs(pk) = l_pk(max) × R_S

   Example: V_rs(pk) = 5.0 × 0.25 = 1.25 V

6. Set independent peak current limit. R_pk1 and R_pk2 are the resistors in the voltage divider. Choose a peak current overload value, I_pk(ovld). A typical value for R_pk1 is 10 kΩ.

V_rs(ovld) = I_pk(olvd) × R_S

Example: V_rs(ovld) = 5.6 × 0.25 = 1.4 V

Equation 31.

Example: R_pk2 = (1.4 × 10kΩ) / 7.5 = 1.87 kΩ. Choose 1.8 kΩ

7. Multiplier setup. The operation of the multiplier is given by the following equation. Imo is the multiplier output current, K_m = 1 , l_ac is the multiplier input current, V_ff is the feedforward voltage and V_vea is the output of the voltage error amplifier.
Equation 32.
1. Feedforward voltage divider. Change V_in from RMS voltage to average voltage of the rectified input voltage. At V_in(min) the voltage at V_ff should be 1.414 V and the voltage at V_ffc, the other divider node, should be about 7.5 V. The average value of V_in is given by the following equation where V_in(min) is the RMS value of the AC input voltage:
Equation 33. V_in(av) = V_in(min) × 0.9

The following two equations are used to find the values for the V_ff divider string. A value of 1 MΩ is usually chosen for the divider input impedance. The two equations must be solved together to get the resistor values.

Equation 34.
Equation 35.

Example: R_ff1 = 910 kΩ, R_ff2 = 91 kΩ, and R_ff3 = 20 kΩ

2. R_vac selection. Find the maximum peak line voltage.
Equation 36. V_pk(max) = √2 × V_in(max)

Example: V_pk(max) = 1.414 × 270 = 382V_pk

Divide by 600 µA, the maximum multiplier input current.

Equation 37.

Example: R_vac = (382) / 6e^–4 = 637 kΩ. Choose 620 kΩ.

3. R_b1 selection. This is the bias resistor. Treat this as a voltage divider with V_ref and R_vac and then solve for R_b1. The equation becomes:

R_b1 = 0.25 R_vac

Example: R_b1 = 0.25R_vac = 155 kΩ. Choose 150 kΩ.

4. R_set selection. I_mo cannot be greater than twice the current through R_set. Find the multiplier input current, l_ac, with V_in(min). Then calculate the value for R_set based on the value of l_ac just calculated.
Equation 38.

Example:

Equation 39.

Example:

Equation 40.

Choose 10 kΩ.

5. R_mo selection. The voltage across R_mo must be equal to the voltage across R_S at the peak current limit at low line input voltage.
Equation 41.

Example: R_mo = (l.25 × 1.12) / (2 × 182e^–6) = 3.84 kΩ.

Choose 3.9 kΩ.

8. Oscillator frequency. Calculate C_t to give the desired switching frequency.
Equation 42.

Example:

Equation 43.
9. Current error amplifier compensation.
   1. Amplifier gain at the switching frequency. Calculate the voltage across the sense resistor due to the inductor current downslope and then divide by the switching frequency. With current transformers substitute (R_S / N) for R_S. The equation is:
   Equation 44.

   Example:

   Equation 45.

   This voltage must equal the peak to peak amplitude of V_S, the voltage on the timing capacitor (5.2 V). The gain of the error amplifier is therefore given by:

   Equation 46.

   Example: G_ca = 5.2 / 1.0 = 5.2

   2. Feedback resistors. Set R_ci equal to R_mo.

   R_ci = R_mo

   R_cz = G_ca × R_ci

   Example: R_cz = 5.2 × 3.9 kΩ =20 kΩ

   3. Current loop crossover frequency.
   Equation 47.

   Example:

   Equation 48.
   4. C_cz selection. Choose a 45° phase margin. Set the zero at the loop crossover frequency.
   Equation 49.

   Example:

   Equation 50.

   Choose 620 pF

   5. C_cp selection. The pole must be above ƒ_S / 2.
   Equation 51.

   Example:

   Equation 52.

   Choose 62 pF.

10. Harmonic distortion budget. Decide on a maximum THD level. Allocate THD sources as necessary. The predominant AC line harmonic is third. Output voltage ripple contributes 1/2% third harmonic to the input current for each 1% ripple at the second harmonic on the output of the error amplifier. The feedforward voltage, V_ff, contributes 1% third harmonic to the input current for each 1% second harmonic at the V_ff input to the UC3854.

Example:

3% third harmonic AC input current is chosen as the specification. 1.5% is allocated to the V_ff input and 0.75% is allocated to the output ripple voltage or 1.5% to V_vao. The remaining 0.75% is allocated to miscellaneous nonlinearities.

11. Voltage error amplifier compensation.
    1. Output ripple voltage. The output ripple is given by the following equation where ƒ_r is the second harmonic ripple frequency:
    Equation 53.

    Example:

    Equation 54.
    2. Amplifier output ripple voltage and gain. V_o(pk) must be reduced to the ripple voltage.
    Equation 55.

    For the UC3854 V_vao is 5 – 1 = 4 V

    Example:

    Equation 56. G_va = (4 × 0.015) / 1.84 = 0.0326
    3. Feedback network values. Find the component values to set the gain of the voltage error amplifier. The value of R_vi is reasonably arbitrary.

    Example: Choose R_vi = 511 kΩ.

    Equation 57.

    Example:

    Equation 58.

    Choose 0.047 µF.

    4. Set DC output voltage.
    Equation 59.

    Example:

    Equation 60.

    Choose 10.0 kΩ.

    5. Find pole frequency. ƒ_vi = unity gain frequency of voltage loop.
    Equation 61.

    Example:

    Equation 62.
    6. Find R_vf.
    Equation 63.

    Example:

    Equation 64.

    Choose 174 kΩ.

12. Feedforward voltage divider capacitors. These capacitors determine the contribution of Vff to the third harmonic distortion on the AC input current. Determine the amount of attenuation needed. The second harmonic content of the rectified line voltage is 66.2%. %THD is the allowed percentage of harmonic distortion budgeted to this input from step 10.
Equation 65.

Example:

Equation 66. G_ff = 1.5 / 66.2 = 0.0227

Use two equal cascaded poles. Find the pole frequencies. fr is the second harmonic ripple frequency.

Equation 67.

Example:

ƒ_p = 0.15 × l20 = 18 Hz

Select C_ff1 and C_ff2.

Equation 68.
Equation 69.

Example:

Equation 70.

Choose 0.10 µF.

Equation 71.

Choose 0.47 µF.