ZHCSET3A November   2015  – December 2015 DS90CR286AT-Q1

PRODUCTION DATA.  

1. 1 特性
2. 2 應用
3. 3 說明
4. 4 修訂歷史記錄
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
   6. 6.6 Switching Characteristics
   7. 6.7 Typical Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 LVDS Receivers
         1. 7.3.1.1 Input Termination
      2. 7.3.2 Phase Locked Loop (PLL)
      3. 7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
      4. 7.3.4 LVCMOS Drivers
   4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
8. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
         1. 8.2.2.1 Bit Resolution and Operating Frequency Compatibility
         2. 8.2.2.2 Data Mapping between Receiver and Endpoint Panel Display
         3. 8.2.2.3 RSKM Interoperability
      3. 8.2.3 Application Curves
9. 9 Power Supply Recommendations
10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
11. 11器件和文檔支持
    1. 11.1 文檔支持
       1. 11.1.1 相關文檔　
    2. 11.2 社區(qū)資源
    3. 11.3 商標
    4. 11.4 靜電放電警告
    5. 11.5 Glossary
12. 12機械、封裝和可訂購信息