產(chǎn)品詳情

Resolution (Bits) 14 Number of DAC channels 1 Interface type Parallel LVDS Sample/update rate (Msps) 400 Features Low Power Rating Space Interpolation 1x Power consumption (typ) (mW) 660 SFDR (dB) 82 Architecture Current Sink Operating temperature range (°C) -55 to 125 Reference type Int
Resolution (Bits) 14 Number of DAC channels 1 Interface type Parallel LVDS Sample/update rate (Msps) 400 Features Low Power Rating Space Interpolation 1x Power consumption (typ) (mW) 660 SFDR (dB) 82 Architecture Current Sink Operating temperature range (°C) -55 to 125 Reference type Int
CFP (HFG) 52 363.474225 mm2 19.065 x 19.065
  • QMLV (QML Class V) MIL-PRF-38535 Qualified, SMD 5962-07204
    • 5962-0720401VXC – Qualified over the Military Temperature Range (–55°C to 125°C)
    • 5962-0720402VXC – Qualified over Reduced Temperature Range (–55°C to 115°C) for Improved Dynamic Performance
  • High-Performance 52-Pin Ceramic Quad Flat Pack (HFG)
  • 400-MSPS Update Rate
  • LVDS-Compatible Input Interface
  • Spurious-Free Dynamic Range (SFDR) to Nyquist
    • 69 dBc at 70 MHz IF, 400 MSPS
  • W-CDMA Adjacent Channel Power Ratio (ACPR)
    • 73 dBc at 30.72 MHz IF, 122.88 MSPS
    • 71 dBc at 61.44 MHz IF, 245.76 MSPS
  • Differential Scalable Current Outputs: 2 to 20 mA
  • On-Chip 1.2-V Reference
  • Single 3.3-V Supply Operation
  • Power Dissipation: 660 mW at ?CLK = 400 MSPS, ?OUT = 20 MHz
  • APPLICATIONS
    • Radiation Hardened Digital to Analog (DAC) Applications
    • Space Satellite RF Data Transmission
    • Cellular Base Transceiver Station Transmit Channel:
      • CDMA: WCDMA, CDMA2000, IS-95
      • TDMA: GSM, IS-136, EDGE/GPRS
      • Supports Single-Carrier and Multicarrier Applications
    • Engineering Evaluation (/EM) Samples are Available(1)

(1) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (for example, no burn-in) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.
All other trademarks are the property of their respective owners
  • QMLV (QML Class V) MIL-PRF-38535 Qualified, SMD 5962-07204
    • 5962-0720401VXC – Qualified over the Military Temperature Range (–55°C to 125°C)
    • 5962-0720402VXC – Qualified over Reduced Temperature Range (–55°C to 115°C) for Improved Dynamic Performance
  • High-Performance 52-Pin Ceramic Quad Flat Pack (HFG)
  • 400-MSPS Update Rate
  • LVDS-Compatible Input Interface
  • Spurious-Free Dynamic Range (SFDR) to Nyquist
    • 69 dBc at 70 MHz IF, 400 MSPS
  • W-CDMA Adjacent Channel Power Ratio (ACPR)
    • 73 dBc at 30.72 MHz IF, 122.88 MSPS
    • 71 dBc at 61.44 MHz IF, 245.76 MSPS
  • Differential Scalable Current Outputs: 2 to 20 mA
  • On-Chip 1.2-V Reference
  • Single 3.3-V Supply Operation
  • Power Dissipation: 660 mW at ?CLK = 400 MSPS, ?OUT = 20 MHz
  • APPLICATIONS
    • Radiation Hardened Digital to Analog (DAC) Applications
    • Space Satellite RF Data Transmission
    • Cellular Base Transceiver Station Transmit Channel:
      • CDMA: WCDMA, CDMA2000, IS-95
      • TDMA: GSM, IS-136, EDGE/GPRS
      • Supports Single-Carrier and Multicarrier Applications
    • Engineering Evaluation (/EM) Samples are Available(1)

(1) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (for example, no burn-in) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.
All other trademarks are the property of their respective owners

The DAC5675A-SP is a radiation-tolerant, 14-bit resolution high-speed digital-to-analog converter (DAC) primarily suited for space satellite applications. The DAC5675A-SP is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A-SP has excellent SFDR at high intermediate frequencies, which makes it well suited for multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs).

The DAC5675A-SP operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at ƒCLK = 400 MSPS, ƒOUT = 70 MHz. The DAC5675A-SP provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD.

The DAC5675A-SP includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels (low electromagnetic interference (EMI)).

LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675A-SP and high-speed low-voltage CMOS ASICs or FPGAs.

The DAC5675A-SP current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing.

The DAC5675A-SP is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD – 1 to AVDD + 0.3 V.

An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to adjust this output current from 20 to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied. The DAC5675A-SP features a SLEEP mode, which reduces the standby power to approximately 18 mW.

The DAC5675A-SP is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The device is specified for operation over the military temperature range of –55°C to 125°C and W temperature range of –55°C to 115°C.

The DAC5675A-SP is a radiation-tolerant, 14-bit resolution high-speed digital-to-analog converter (DAC) primarily suited for space satellite applications. The DAC5675A-SP is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A-SP has excellent SFDR at high intermediate frequencies, which makes it well suited for multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs).

The DAC5675A-SP operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at ƒCLK = 400 MSPS, ƒOUT = 70 MHz. The DAC5675A-SP provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD.

The DAC5675A-SP includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels (low electromagnetic interference (EMI)).

LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675A-SP and high-speed low-voltage CMOS ASICs or FPGAs.

The DAC5675A-SP current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing.

The DAC5675A-SP is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD – 1 to AVDD + 0.3 V.

An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to adjust this output current from 20 to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied. The DAC5675A-SP features a SLEEP mode, which reduces the standby power to approximately 18 mW.

The DAC5675A-SP is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The device is specified for operation over the military temperature range of –55°C to 125°C and W temperature range of –55°C to 115°C.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 DAC5675A-SP Radiation-Tolerant, 14-Bit, 400-MSPS Digital-to-Analog Converter 數(shù)據(jù)表 (Rev. H) PDF | HTML 2016年 8月 4日
* 輻射與可靠性報告 ICS Radiation Test Results TI-DAC5675A-SP 14-Bit DAC 2021年 1月 7日
* SMD DAC5675A-SP SMD 5962-07204 2016年 7月 8日
* 輻射與可靠性報告 DAC5675A SEE Report 2015年 3月 31日
應(yīng)用簡報 經(jīng) DLA 批準(zhǔn)的 QML 產(chǎn)品優(yōu)化 (Rev. C) PDF | HTML 英語版 (Rev.C) PDF | HTML 2025年 8月 18日
應(yīng)用手冊 重離子軌道環(huán)境單粒子效應(yīng)估算 (Rev. B) PDF | HTML 英語版 (Rev.B) PDF | HTML 2025年 7月 7日
選擇指南 TI Space Products (Rev. K) 2025年 4月 4日
更多文獻(xiàn)資料 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025年 2月 20日
應(yīng)用手冊 單粒子效應(yīng)置信區(qū)間計算 (Rev. A) PDF | HTML 英語版 (Rev.A) PDF | HTML 2022年 12月 2日
電子書 電子產(chǎn)品輻射手冊 (Rev. B) 2022年 5月 7日
電子書 電子產(chǎn)品輻射手冊 (Rev. A) 2019年 5月 21日
應(yīng)用手冊 High Speed, Digital-to-Analog Converters Basics (Rev. A) 2012年 10月 23日
應(yīng)用手冊 所選封裝材料的熱學(xué)和電學(xué)性質(zhì) 2008年 10月 16日
應(yīng)用手冊 高速數(shù)據(jù)轉(zhuǎn)換 英語版 2008年 10月 16日
應(yīng)用手冊 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
應(yīng)用手冊 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日

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