DS100KR401
The DS100KR401 is an extremely low power, high performance repeater designed to support 4 lane (bi-directional) 10G-KR and other high speed interface serial protocols up to 10.3 Gbps. The receiver's continuous time linear equalizer (CTLE) provides a boost of up to +36 dB at 5 GHz (10.3125 Gbps) in each of its eight channels and is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as long backplanes or cables, hence enabling host controllers to ensure an error free end-to-end link. The transmitter provides a de-emphasis boost of up to -12 dB and output voltage amplitude control from 700 mV to 1300 mV to allow maximum flexibility in the physical placement within the interconnect channel.
When operating in 10G-KR mode, the DS100KR401 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients as defined in the 802.3ap standard. This seamless management of the link training protocol ensures guaranteed system level interoperability with minimum latency.
With a low power consumption of 65 mW/channel (typ) and option to turn-off unused channels, the DS100KR401 enables energy efficient system design. A single supply of 3.3v or 2.5v is required to power the device.
The programmable settings can be applied via pin settings, SMBus (I2C) protocol or an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up. This eliminates the need for an external microprocessor or software driver.
技術(shù)文檔
| 頂層文檔 | 類型 | 標(biāo)題 | 格式選項 | 下載最新的英語版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | DS100KR401 Ultra Low Power 4 Lane Advanced Repeater for 10G-KR 數(shù)據(jù)表 (Rev. B) | 2012年 3月 22日 | |||
| 應(yīng)用手冊 | 利用適用于 10G 至 12.5G 應(yīng)用的以太網(wǎng)轉(zhuǎn)接驅(qū)動器和重定時器來擴(kuò)大覆蓋范圍 (Rev. A) | PDF | HTML | 英語版 (Rev.A) | 2023年 2月 12日 | ||
| 應(yīng)用手冊 | Understanding EEPROM Programming for High Speed Repeaters and Mux Buffers | 2014年 10月 9日 | ||||
| 用戶指南 | DS100KR401EVK User's Guide: 4 Channels SMA Evaluation Kit | 2013年 10月 25日 | ||||
| 設(shè)計指南 | 適用于 Xilinx FPGA 的模擬器件 解決方案指南 | 2012年 4月 24日 |
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