DS25BR101
- DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
- Receive Equalization Reduces ISI Jitter Due to Media Loss
- Transmit Pre-Emphasis Drives Lossy Backplanes and Cables
- On-Chip 100? Input and Output Termination:
- Minimizes Insertion and Return Losses
- Reduces Component Count
- Minimizes Board Space
- DS25BR101 Eliminates On-Chip Input Termination for Added Design Flexibility
- 7 kV ESD on LVDS I/O Pins Protects Adjoining Components
- Small 3 mm x 3 mm WSON-8 Space Saving Package
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The DS25BR100 and DS25BR101 are single channel 3.125 Gbps LVDS buffers optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.
The DS25BR100 and DS25BR101 feature transmit pre-emphasis (PE) and receive equalization (EQ), making them ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. On the DS25BR100 the differential input and output is internally terminated with a 100? resistor to lower return losses, reduce component count and further minimize board space. For added design flexibility the 100? input terminations on the DS25BR101 have been eliminated. This elimination enables a designer to adjust the termination for custom interconnect topologies and layout.
技術(shù)文檔
| 頂層文檔 | 類(lèi)型 | 標(biāo)題 | 格式選項(xiàng) | 下載最新的英語(yǔ)版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | DS25BR100/101 3.125Gbps LVDS Buffer w/Transmit Pre-Empha & Rcve Equalization 數(shù)據(jù)表 (Rev. F) | 2013年 4月 14日 | |||
| 應(yīng)用手冊(cè) | 低壓差分信號(hào) (LVDS) 在 LED 燈墻中的應(yīng)用 | 英語(yǔ)版 | 2022年 5月 19日 | |||
| 應(yīng)用手冊(cè) | Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners | 2019年 6月 29日 |
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| 封裝 | 引腳 | CAD 符號(hào)、封裝和 3D 模型 |
|---|---|---|
| WSON (NGQ) | 8 | Ultra Librarian |
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