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DS90CR286A-Q1

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+3.3V 上升沿數(shù)據(jù)選通 LVDS 28 位汽車類 Channel Link 接收器 - 66MHz

產(chǎn)品詳情

Applications In-vehicle Infotainment (IVI) Input compatibility LVDS Function Deserializer Output compatibility LVCMOS Color depth (bpp) 24 Features Low-EMI Point-to-Point Communication EMI reduction LVDS Rating Automotive Operating temperature range (°C) -40 to 85
Applications In-vehicle Infotainment (IVI) Input compatibility LVDS Function Deserializer Output compatibility LVCMOS Color depth (bpp) 24 Features Low-EMI Point-to-Point Communication EMI reduction LVDS Rating Automotive Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm2 14 x 8.1
  • 20 to 66 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best–in–Class Set and Hold Times on Rx Outputs
  • Rx Power Consumption < 270 mW (Typ) at 66
    MHz Worst Case
  • Rx Power-Down Mode < 200 μW (Max)
  • ESD Rating > 7 kV (HBM), > 700 V (EIAJ)
  • PLL Requires No External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Pin or 48-Pin DGG (TSSOP)
    Package
  • Operating Temperature: ?40°C to 85°C
  • Automotive Q Grade Available – AEC-Q100 Grade
    3 Qualified
  • 20 to 66 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best–in–Class Set and Hold Times on Rx Outputs
  • Rx Power Consumption < 270 mW (Typ) at 66
    MHz Worst Case
  • Rx Power-Down Mode < 200 μW (Max)
  • ESD Rating > 7 kV (HBM), > 700 V (EIAJ)
  • PLL Requires No External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Pin or 48-Pin DGG (TSSOP)
    Package
  • Operating Temperature: ?40°C to 85°C
  • Automotive Q Grade Available – AEC-Q100 Grade
    3 Qualified

The DS90CR286A receiver converts the four LVDS data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CR216A receiver that converts the three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the rising edge.

The receiver LVDS clock operates at rates from 20 to 66 MHz. The device phase-locks to the input clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps for the DS90CR286A and 1.386 Gbps for the DS90CR216A.

The DS90CR286A and DS90CR216A devices are enhanced over prior generation receivers and provide a wider data valid time on the receiver output. The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages.

The DS90CR286A receiver converts the four LVDS data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CR216A receiver that converts the three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the rising edge.

The receiver LVDS clock operates at rates from 20 to 66 MHz. The device phase-locks to the input clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps for the DS90CR286A and 1.386 Gbps for the DS90CR216A.

The DS90CR286A and DS90CR216A devices are enhanced over prior generation receivers and provide a wider data valid time on the receiver output. The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages.
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頂層文檔 類型 標題 格式選項 下載最新的英語版本 日期
* 數(shù)據(jù)表 DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz 數(shù)據(jù)表 (Rev. H) PDF | HTML 2016年 1月 18日
應(yīng)用手冊 Receiver Skew Margin for Channel Link I and FPD Link I Devices 2016年 1月 13日
設(shè)計指南 Channel Link I Design Guide 2007年 3月 29日
應(yīng)用手冊 Multi-Drop Channel-Link Operation 2004年 10月 4日
應(yīng)用手冊 CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications 1998年 10月 5日

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TSSOP (DGG) 56 Ultra Librarian

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