DS90LV018A
- >400 Mbps (200 MHz) Switching Rates
- 50 ps Differential Skew (Typical)
- 2.5 ns Maximum Propagation Delay
- 3.3V Power Supply Design
- Flow-Through Pinout
- Power Down High Impedance on LVDS Inputs
- Low Power Design (18mW @ 3.3V Static)
- Interoperable with Existing 5V LVDS Networks
- Accepts Small Swing (350 mV Typical) Differential Signal Levels
- Supports Open, Short and Terminated Input Fail-Safe
- Conforms to ANSI/TIA/EIA-644 Standard
- Industrial Temperature Operating Range
- (?40°C to +85°C)
- Available in SOIC Package
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The DS90LV018A is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.
The DS90LV018A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver also supports open, shorted and terminated (100Ω) input fail-safe. The receiver output will be HIGH for all fail-safe conditions. The DS90LV018A has a flow-through design for easy PCB layout.
The DS90LV018A and companion LVDS line driver provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.
技術(shù)文檔
| 頂層文檔 | 類型 | 標(biāo)題 | 格式選項(xiàng) | 下載最新的英語(yǔ)版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | DS90LV018A 3V LVDS Single CMOS Differential Line Receiver 數(shù)據(jù)表 (Rev. D) | 2013年 4月 16日 | |||
| 應(yīng)用簡(jiǎn)報(bào) | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||||
| 應(yīng)用簡(jiǎn)報(bào) | DACx1416 Delivers Optimized Solution to Mach Zehnder Modulator Biasing | 2018年 6月 29日 | ||||
| 應(yīng)用手冊(cè) | An Overview of LVDS Technology | 1998年 10月 5日 |
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| 封裝 | 引腳 | CAD 符號(hào)、封裝和 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
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