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LP2996A

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具有 DDR2/3/3L 關斷引腳的 1.5A DDR 終端穩(wěn)壓器

產(chǎn)品詳情

Product type DDR Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) 0 to 125 Iq (typ) (mA) 0.32 DDR memory type DDR, DDR2, DDR3, DDR3L
Product type DDR Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) 0 to 125 Iq (typ) (mA) 0.32 DDR memory type DDR, DDR2, DDR3, DDR3L
HSOIC (DDA) 8 29.4 mm2 4.9 x 6
  • Minimum VDDQ:
    • 1.8 V (LP2996-N)
    • 1.35 V (LP2996A)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required for Setting Output Voltage
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Stable With Ceramic Capacitors With Appropriate ESR
  • Low External Component Count
  • Thermal Shutdown
  • Minimum VDDQ:
    • 1.8 V (LP2996-N)
    • 1.35 V (LP2996A)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required for Setting Output Voltage
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Stable With Ceramic Capacitors With Appropriate ESR
  • Low External Component Count
  • Thermal Shutdown

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996-N and LP2996A is an active-low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices for automotive applications and DDR applications that require operating at temperatures below zero.

WEBENCH® design tools can be used by application designers to generate, optimize, and simlulate applications using the LP2998 and LP2998-Q1.

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996-N and LP2996A is an active-low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices for automotive applications and DDR applications that require operating at temperatures below zero.

WEBENCH® design tools can be used by application designers to generate, optimize, and simlulate applications using the LP2998 and LP2998-Q1.
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頂層文檔 類型 標題 格式選項 下載最新的英語版本 日期
* 數(shù)據(jù)表 LP2996/LP2996A DDR Termination Regulator 數(shù)據(jù)表 (Rev. K) 2016年 12月 23日
應用手冊 Limiting DDR Termination Regulators’ Inrush Current 2016年 8月 23日

設計與開發(fā)

如需其他信息或資源，請點擊以下任一標題進入詳情頁面查看（如有）。

評估板

LP2998EVAL — 用于 LP2998 的評估板

The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.

用戶指南: PDF
TI.com 上無現(xiàn)貨
仿真模型

LP2996A PSpice Transient Model

SNOM562.ZIP (85 KB) - PSpice Model
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仿真模型

LP2996A Unencrypted PSpice Transient Model

SNOM564.ZIP (7 KB) - PSpice Model
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參考設計

TIDA-010011 — 適用于保護繼電器處理器模塊的高效電源架構參考設計

該參考設計展示了各種電源架構，這些架構可為需要 >1A 負載電流和高效率的應用處理器模塊生成多個電壓軌。所需的電源通過來自背板的 5V、12V 或 24V 直流輸入生成。電源通過帶集成 FET 的直流/直流轉換器生成并且使用帶集成電感器的電源模塊以減小尺寸。此設計采用 HotRod? 封裝類型，適用于需要低 EMI 的應用，也非常適合設計時間受限的應用。其他功能包括 DDR 端接穩(wěn)壓器、輸入電源 OR-ing、電壓時序控制、過載保護電子保險絲以及電壓和負載電流監(jiān)控。該設計可以用于處理器、數(shù)字信號處理器和現(xiàn)場可編程門陣列。該設計已依照 CISPR22 標準針對輻射發(fā)射進行了測試，符合 A (...)
原理圖: PDF
參考設計

TIDEP0067 — 66AK2Gx DSP + ARM 處理器電源解決方案參考設計

此參考設計基于 66AK2Gx 多內(nèi)核片上系統(tǒng) (SoC) 處理器和配套 TPS65911 電源管理集成電路 (PMIC)，該電路在單個器件中包含適用于 66AK2Gx 處理器的電源和電源定序。該電源解決方案的設計還包含支持 12V 輸入的第一級降壓轉換器和 DDR3L 存儲器的 DDR 終端穩(wěn)壓器。該參考設計經(jīng)過了測試、包括硬件參考 (EVM)、軟件（處理器 SDK）和測試數(shù)據(jù)。
設計指南: PDF
原理圖: PDF
封裝 引腳 CAD 符號、封裝和 3D 模型
HSOIC (DDA) 8 Ultra Librarian

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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