SN74ALVCH16374

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具有三態(tài)輸出的 16 位邊沿 D 類(lèi)觸發(fā)器

產(chǎn)品詳情

Number of channels 16 Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (μA) 40 Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 16 Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (μA) 40 Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DL) 48 164.358 mm2 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm2 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm2 9.7 x 6.4
  • Member of the Texas Instruments Widebus? Family
  • Operates From 1.65 to 3.6 V
  • Max tpd of 4.2 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus? Family
  • Operates From 1.65 to 3.6 V
  • Max tpd of 4.2 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE\ can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE\ can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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頂層文檔 類(lèi)型 標(biāo)題 格式選項(xiàng) 下載最新的英語(yǔ)版本 日期
* 數(shù)據(jù)表 SN74ALVCH16374 數(shù)據(jù)表 (Rev. L) 2004年 9月 7日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 2025年 11月 13日
應(yīng)用手冊(cè) Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
應(yīng)用手冊(cè) An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018年 9月 17日
應(yīng)用手冊(cè) Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語(yǔ)版本 (Rev.AC) PDF | HTML 2014年 11月 17日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應(yīng)用手冊(cè) Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
應(yīng)用手冊(cè) TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
用戶指南 ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002年 8月 1日
更多文獻(xiàn)資料 Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
應(yīng)用手冊(cè) 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
應(yīng)用手冊(cè) Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
應(yīng)用手冊(cè) TI SN74ALVC16835 Component Specification Analysis for PC100 1998年 8月 3日
應(yīng)用手冊(cè) Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998年 5月 13日
應(yīng)用手冊(cè) Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
應(yīng)用手冊(cè) Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
應(yīng)用手冊(cè) CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
應(yīng)用手冊(cè) Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
應(yīng)用手冊(cè) Live Insertion 1996年 10月 1日
應(yīng)用手冊(cè) Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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仿真模型

HSPICE Model for SN74ALVCH16374

SCEJ206.ZIP (285 KB) - HSpice Model
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仿真模型

SN74ALVCH16374 IBIS Model (Rev. A)

SCEM034A.ZIP (6 KB) - IBIS Model
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參考設(shè)計(jì)

TIDEP0054 — 適用于變電站自動(dòng)化的并行冗余協(xié)議 (PRP) 以太網(wǎng)參考設(shè)計(jì)

此參考設(shè)計(jì)為智能電網(wǎng)輸電和配電網(wǎng)絡(luò)中的變電站自動(dòng)化設(shè)備提供高可靠性、低延遲網(wǎng)絡(luò)通信。它支持 IEC 62439 標(biāo)準(zhǔn)中使用 PRU-ICSS 的并行冗余協(xié)議 (PRP) 規(guī)范。此參考設(shè)計(jì)是 FPGA 方法的較低成本替代方法，可提供在無(wú)需額外組件的情況下添加 IEC 61850 支持等功能的靈活性和性能。
設(shè)計(jì)指南: PDF
原理圖: PDF
參考設(shè)計(jì)

TIDEP0043 — Acontis EtherCAT 主站協(xié)議棧參考設(shè)計(jì)

Acontis EC-Master EtherCAT Master 堆棧是一種可移植度非常高的軟件堆棧，可在各種嵌入式平臺(tái)上使用。EC-Master 支持高性能的 TI Sitara MPU，可提供先進(jìn)的 EtherCAT Master 解決方案，客戶可使用該解決方案來(lái)實(shí)施 EtherCAT 通信接口電路板、基于 EtherCAT 的 PLC 或運(yùn)動(dòng)控制應(yīng)用。EC-Master 結(jié)構(gòu)設(shè)計(jì)讓用戶無(wú)需計(jì)劃額外的任務(wù)，因此即使在沒(méi)有操作系統(tǒng)的平臺(tái)（例如 AM335x 上支持的 TI Starterware）上也可以使用全部堆棧功能。這種架構(gòu)結(jié)合高速以太網(wǎng)驅(qū)動(dòng)器讓用戶能在 Sitara 平臺(tái)上實(shí)施 (...)
設(shè)計(jì)指南: PDF
原理圖: PDF
封裝 引腳 CAD 符號(hào)、封裝和 3D 模型
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian

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包含信息：
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  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息：
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  • 封裝廠地點(diǎn)

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