SN74AUP1T157

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低功耗、1.8/2.5/3.3V 輸入、3.3V CMOS 輸出、緩沖多路復(fù)用器（非反向）

產(chǎn)品詳情

Technology family AUP1T Number of channels 1 Vout (min) (V) 2.3 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) 4 Supply current (max) (μA) 0.9 Features Over-voltage tolerant inputs, Partial power down (Ioff), Single supply, Voltage translation Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 85
Technology family AUP1T Number of channels 1 Vout (min) (V) 2.3 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) 4 Supply current (max) (μA) 0.9 Features Over-voltage tolerant inputs, Partial power down (Ioff), Single supply, Voltage translation Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 85
SOT-SC70 (DCK) 6 4.2 mm2 2 x 2.1
  • Single-Supply Voltage Translator
  • Output Level Up to Supply VCC CMOS Level
    • 1.8 V to 3.3 V (at VCC = 3.3 V)
    • 2.5 V to 3.3 V (at VCC = 3.3 V)
    • 1.8 V to 2.5 V (at VCC = 2.5 V)
    • 3.3 V to 2.5 V (at VCC = 2.5 V
  • Schmitt-Trigger Inputs Reject Input Noise and Provide
    Better Output Signal Integrity
  • Ioff Supports Partial Power Down (VCC = 0 V)
  • Very Low Static Power Consumption:
    0.1 μA
  • Very Low Dynamic Power Consumption:
    0.9 μA
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Pb-Free Packages Available: SC-70 (DCK)
    2 x 2.1 x 0.65 mm (Height 1.1 mm)
  • More Gate Options Available at www.ti.com/littlelogic
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Single-Supply Voltage Translator
  • Output Level Up to Supply VCC CMOS Level
    • 1.8 V to 3.3 V (at VCC = 3.3 V)
    • 2.5 V to 3.3 V (at VCC = 3.3 V)
    • 1.8 V to 2.5 V (at VCC = 2.5 V)
    • 3.3 V to 2.5 V (at VCC = 2.5 V
  • Schmitt-Trigger Inputs Reject Input Noise and Provide
    Better Output Signal Integrity
  • Ioff Supports Partial Power Down (VCC = 0 V)
  • Very Low Static Power Consumption:
    0.1 μA
  • Very Low Dynamic Power Consumption:
    0.9 μA
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Pb-Free Packages Available: SC-70 (DCK)
    2 x 2.1 x 0.65 mm (Height 1.1 mm)
  • More Gate Options Available at www.ti.com/littlelogic
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

The SN74AUP1T157 is a single 2-input multiplexer that selects data from two data inputs (A and B) under control of a common data select input (C). The state of the common data select input determines the particular register from which the data comes. The output (Y) presents the selected data in the true (non-inverted) form.

AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 2 and Figure 3).

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T157 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

The SN74AUP1T157 is a single 2-input multiplexer that selects data from two data inputs (A and B) under control of a common data select input (C). The state of the common data select input determines the particular register from which the data comes. The output (Y) presents the selected data in the true (non-inverted) form.

AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 2 and Figure 3).

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T157 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
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* 數(shù)據(jù)表 Low Power, 1.8/2.5/3.3-V In, 3.3-V CMOS Out, Buffer Multiplexer (Noninverted) 數(shù)據(jù)表 2010年 4月 16日
應(yīng)用簡(jiǎn)報(bào) 了解施密特觸發(fā)器 (Rev. B) PDF | HTML 英語(yǔ)版 (Rev.B) PDF | HTML 2025年 5月 5日
選擇指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日

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SOT-SC70 (DCK) 6 Ultra Librarian

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