產(chǎn)品詳情

Bits (#) 1 Data rate (max) (Mbps) 200 Topology Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 2.3 Vin (max) (V) 3.6 Applications GPIO Features Partial power down (Ioff), Single supply Technology family AUP1T Supply current (max) (mA) 0.0036 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 1 Data rate (max) (Mbps) 200 Topology Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 2.3 Vin (max) (V) 3.6 Applications GPIO Features Partial power down (Ioff), Single supply Technology family AUP1T Supply current (max) (mA) 0.0036 Rating Catalog Operating temperature range (°C) -40 to 85
SOT-SC70 (DCK) 5 4.2 mm2 2 x 2.1
  • Single-Supply Voltage Translator
  • Output Level Up to Supply VCC CMOS Level
    • 1.8 V to 3.3 V (at VCC = 3.3 V)
    • 2.5 V to 3.3 V (at VCC = 3.3 V)
    • 1.8 V to 2.5 V (at VCC = 2.5 V)
    • 3.3 V to 2.5 V (at VCC = 2.5 V
  • Schmitt-Trigger Inputs Reject Input Noise and
    Provide Better Output Signal Integrity
  • Ioff Supports Partial Power Down (VCC = 0 V)
  • Very Low Static Power Consumption:
    0.1 μA
  • Very Low Dynamic Power Consumption:
    0.9 μA
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • Pb-Free Packages Available: SC-70 (DCK)

    2 × 2.1 × 0.65 mm (Height 1.1 mm)
  • More Gate Options Available at
    www.ti.com/littlelogic
  • ESD Performance Tested Per JESD 22
    • 2000-V Human Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • AV Receivers
    • Audio Dock: Portable
    • Blu-ray Players and Home Theaters
    • MP3 Players and Recorders
    • Personal Digital Assistant (PDA)
    • Power: Telecom/Server AC/DC Supply: Single
      Controller: Analog and Digital
    • Solid State Drive (SSD): Client and Enterprise
    • TV: LCD/Digital and High-Definition (HDTV)
    • Tablet: Enterprise
    • Video Analytics: Servers
    • Wireless Headsets, Keyboards, and Mice

All other trademarks are the property of their respective owners
  • Single-Supply Voltage Translator
  • Output Level Up to Supply VCC CMOS Level
    • 1.8 V to 3.3 V (at VCC = 3.3 V)
    • 2.5 V to 3.3 V (at VCC = 3.3 V)
    • 1.8 V to 2.5 V (at VCC = 2.5 V)
    • 3.3 V to 2.5 V (at VCC = 2.5 V
  • Schmitt-Trigger Inputs Reject Input Noise and
    Provide Better Output Signal Integrity
  • Ioff Supports Partial Power Down (VCC = 0 V)
  • Very Low Static Power Consumption:
    0.1 μA
  • Very Low Dynamic Power Consumption:
    0.9 μA
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • Pb-Free Packages Available: SC-70 (DCK)

    2 × 2.1 × 0.65 mm (Height 1.1 mm)
  • More Gate Options Available at
    www.ti.com/littlelogic
  • ESD Performance Tested Per JESD 22
    • 2000-V Human Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • AV Receivers
    • Audio Dock: Portable
    • Blu-ray Players and Home Theaters
    • MP3 Players and Recorders
    • Personal Digital Assistant (PDA)
    • Power: Telecom/Server AC/DC Supply: Single
      Controller: Analog and Digital
    • Solid State Drive (SSD): Client and Enterprise
    • TV: LCD/Digital and High-Definition (HDTV)
    • Tablet: Enterprise
    • Video Analytics: Servers
    • Wireless Headsets, Keyboards, and Mice

All other trademarks are the property of their respective owners

The SN74AUP1T17 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC.

AUP technology is the industry–s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity.

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T17 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

The SN74AUP1T17 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC.

AUP technology is the industry–s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity.

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T17 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
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* 數(shù)據(jù)表 SN74AUP1T17 Low Power, 1.8/2.5/3.3-V Input, 3.3-V CMOS Output, Single Schmitt-Trigger Buffer Gate 數(shù)據(jù)表 (Rev. A) PDF | HTML 2015年 6月 30日
應用簡報 了解施密特觸發(fā)器 (Rev. B) PDF | HTML 英語版 (Rev.B) PDF | HTML 2025年 5月 5日
應用手冊 原理圖檢查清單 - 使用自動雙向轉換器進行設計的指南 PDF | HTML 英語版 PDF | HTML 2024年 12月 3日
應用手冊 原理圖檢查清單 - 使用固定或方向控制轉換器進行設計的指南 PDF | HTML 英語版 PDF | HTML 2024年 10月 3日
應用手冊 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
應用手冊 了解 CMOS 輸出緩沖器中的瞬態(tài)驅動強度與直流驅動強度 PDF | HTML 最新英語版本 (Rev.A) PDF | HTML 2024年 5月 15日
選擇指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日

設計與開發(fā)

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評估板

5-8-LOGIC-EVM — 支持 5 至 8 引腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模塊

靈活的 EVM 設計用于支持具有 5 至 8 引腳數(shù)且采用 DCK、DCT、DCU、DRL 或 DBV 封裝的任何器件。
用戶指南: PDF
TI.com 上無現(xiàn)貨
參考設計

TIDA-00268 — Thunderbolt™ 單端口外設參考設計

TI Thunderbolt? 單端口外設參考設計已針對具有 20Gbps 帶寬的 Thunderbolt 2 系統(tǒng)進行優(yōu)化。此設計利用 TPS65980 電源管理單元，與離散式實施相比，可將 BOM 成本降低達 50%，將面積降低約 40%。此設計已在 Intel 針對自供電和總線供電的單端口 Thunderbolt 系統(tǒng)進行測試和認證。
設計指南: PDF
原理圖: PDF
封裝 引腳 CAD 符號、封裝和 3D 模型
SOT-SC70 (DCK) 5 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

支持和培訓

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