TRF371109
- Frequency Range: 300 MHz to 1700 MHz
- Integrated Baseband Programmable Gain Amplifier
- On-Chip Programmable Baseband Filter
- High Cascaded IP3: 27 dBm at 900 MHz
- High IP2: 68 dBm at 900 MHz
- Hardware and Software Power Down
- Three-Wire Serial Interface
- Single Supply: 4.5-V to 5.5-V Operation
- Silicon Germanium Technology
- APPLICATIONS
- Multicarrier Wireless Infrastructure
- WiMAX
- High-Linearity Direct-Downconversion Receiver
- LTE (Long Term Evolution)
All other trademarks are the property of their respective owners.
The TRF371109 is a highly linear direct-conversion quadrature receiver. The TRF371109 integrates balanced I and Q mixers, LO buffers, and phase splitters to convert an RF signal directly to I and Q baseband. The on-chip programmable gain amplifiers allow adjustment of the output signal level without the need for external variable gain (attenuator) devices. The TRF371109 integrates programmable baseband low-pass filters that attenuate nearby interference, eliminating the need for an external baseband filter.
Housed in a 7-mm × 7-mm VQFN package, the TRF371109 provides the smallest and most integrated receiver solution available for high-performance equipment.
技術(shù)文檔
| 頂層文檔 | 類型 | 標(biāo)題 | 格式選項(xiàng) | 下載最新的英語版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | Direct Downconversion Receiver 數(shù)據(jù)表 (Rev. B) | 2011年 5月 10日 | |||
| 技術(shù)文章 | Can a clock generator act as a jitter cleaner? | PDF | HTML | 2017年 3月 23日 | |||
| 技術(shù)文章 | Don’t let bad reference signals destroy the phase noise in your PLL/synthesizer | PDF | HTML | 2017年 1月 10日 | |||
| 技術(shù)文章 | A survival guide to scaling your PLL loop filter design | PDF | HTML | 2016年 11月 22日 | |||
| 技術(shù)文章 | What to do when your PLL does not lock | PDF | HTML | 2016年 7月 12日 | |||
| 技術(shù)文章 | Issues with jitter, phase noise, lock time or spurs? Check the loop-filter bandwid | PDF | HTML | 2016年 6月 6日 | |||
| 應(yīng)用手冊(cè) | Characterization Report for FMC30RF | 2014年 9月 18日 | ||||
| 設(shè)計(jì)指南 | 適用于 Xilinx FPGA 的模擬器件 解決方案指南 | 2012年 4月 24日 | ||||
| 應(yīng)用手冊(cè) | DC Offset Auto-Calibration of TRF371x | 2009年 11月 5日 |
設(shè)計(jì)與開發(fā)
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TRF371109EVM — TRF371109 評(píng)估模塊
| 封裝 | 引腳 | CAD 符號(hào)、封裝和 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購(gòu)和質(zhì)量
- RoHS
- REACH
- 器件標(biāo)識(shí)
- 引腳鍍層/焊球材料
- MSL 等級(jí)/回流焊峰值溫度
- MTBF/時(shí)基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測(cè)
- 制造廠地點(diǎn)
- 封裝廠地點(diǎn)