ZHCSK81A September 2019 – October 2020 TPS65296
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INPUT SUPPLY VOLTAGE | ||||||
| IVCC_5V | VCC_5V supply current | VVDD_EN = VVDDQ_EN = 0 V | 5 | μA | ||
| VVDD_EN = 5 V, VVDDQ_EN = 0 V, no load | 110 | μA | ||||
| VVDD_EN = VVDDQ_EN = 5 V, no load | 150 | μA | ||||
| VIN | PVIN input voltage range | 4.5 | 18 | V | ||
| UVLO | ||||||
| UVLO | VCC_5V under-voltage lockout | Wake up VCC_5V voltage | 4.1 | 4.5 | V | |
| Shut down VCC_5V voltage | 3.3 | 3.6 | V | |||
| Hysteresis VCC_5V voltage | 500 | mV | ||||
| VDD2 | ||||||
| VVDD2SNS | VDD2 sense voltage | 1.1 | 1.115 | 1.13 | V | |
| IVDD2SNS | VDD2SNS input current | VVDD2SNS =1.1 V | 40 | μA | ||
| IVDD2DIS | VDD2 discharge current | VVDD_EN = VVDDQ_EN = 0 V, VVDD2SNS = 0.5 V | 12 | mA | ||
| tVDD2SS | VDD2 soft-start time | 1.6 | 2.65 | ms | ||
| tVDD2DLY | VDD2 ramp up delay time | 1.3 | 2 | 3.5 | ms | |
| RDSONH | High-side switch resistance | TJ = 25°C, VVCC_5V = 5V | 22 | mΩ | ||
| RDSONL | Low-side switch resistance | TJ = 25°C, VVCC_5V = 5V | 8.6 | mΩ | ||
| IVDD2OCL | Low-side valley current limited | VOUT = 1.1 V, L = 0.68 μH | 8.2 | 9.8 | 11.5 | A |
| fsw | VDD2 switching freqency | 600 | kHz | |||
| tOFF(MIN) | Minimum off time | 198 | ns | |||
| PGOOD (VDD2, VDD1) | ||||||
| VTHPG | PGOOD threshold | VDD2SNS / VDD1SNS falling (Fault) | 87 | % | ||
| VDD2SNS / VDD1SNS rising (Good) | 93 | % | ||||
| VDD2SNS / VDD1SNS rising (Fault) | 115 | % | ||||
| VDD2SNS / VDD1SNS falling (Good) | 110 | % | ||||
| IPGMAX | PG sink current | VPGOOD =0.5V, VVDD_EN =VVDDQ_EN = 5 V, no load | 46 | mA | ||
| tPGDLY | PG start-up delay | PG from low to high | 1 | ms | ||
| VDD1 | ||||||
| VVDD1SNS | VDD1 sense voltage | 1.75 | 1.8 | 1.85 | V | |
| IVDD1SNS | VDD1SNS input current | VVDD1SNS =1.8 V | 20 | μA | ||
| IVDD1DIS | VDD1 discharge current | VVDD_EN = VVDDQ_EN = 0 V, VVDD1SNS = 0.5 V | 12 | mA | ||
| tVDD1SS | VDD1 soft-start time | 1.0 | 2 | ms | ||
| RDSONH | High-side switch resistance | TJ = 25°C, VPVIN_VDD1 = 5V, VVCC_5V = 5V | 150 | mΩ | ||
| RDSONL | Low-side switch resistance | TJ = 25°C, VPVIN_VDD1=5V, VVCC_5V = 5V | 120 | mΩ | ||
| IVDD1OCL | Low-side valley current limited | VVDD1SNS = 1.8 V, L = 4.7 μH | 1.05 | 1.6 | 2.1 | A |
| fsw | VDD1 switching frequency | 580 | kHz | |||
| tOFF(MIN) | Minimum off time | 195 | ns | |||
| tOOA | OOA mode operation period | VVDD1SNS =1.8 V | 31 | μs | ||
| OVP AND UVP (VDD2, VDD1) | ||||||
| VOVP | OVP threshold voltage | OVP detect voltage | 120 | 125 | 130 | % |
| VUVP1 | UVP threshold voltage | UVP detect voltage | 57.5 | 62.5 | 67.5 | % |
| tOVPDLY | OVP delay | 20 | μs | |||
| tUVPDLY | UVP delay | 250 | μs | |||
| VDDQ OUTPUT | ||||||
| VVDDQ | Output voltage | TJ = 25°C, IVDDQ ≤1.5A | 0.57 | 0.6 | 0.63 | V |
| IVDDQOCLSRC | Source current limit | VVDD2SNS = 1.1 V, VVDDQ= VVDDQSNS= 0.5 V | 1.7 | 2.2 | A | |
| IVDDQLK | Leakage current | TJ = 25°C, VVDD_EN = 5 V, VVDDQ_EN = 5 V | 5 | μA | ||
| IVDDQSNSBIAS | VDDQSNS input bias current | VVDD_EN = 5 V, VVDDQ_EN = 5 V | –0.5 | 0 | 0.5 | |
| IVDDQSNSLK | VDDQSNS leakage current | VVDD_EN = 5 V, VVDDQ_EN = 0 V | –1 | 0 | 1 | |
| IVDDQDLY | VDDQ output delay relative to VDDQ_EN | 35 | us | |||
| IVDDQDIS | VDDQ discharge current | TJ = 25°C, VVDD_EN = VVDDQ_EN = 0 V, VVDD2SNS = 1.1 V, VVDDQ =0.5V | 5.7 | mA | ||
| VDD_EN, VDDQ_EN LOGIC THRESHOLD | ||||||
| VIH | VDD_EN/VDDQ_EN high-level voltage | 1.35 | V | |||
| VIL | VDD_EN/VDDQ_EN low-level voltage | 0.5 | V | |||
| RTOGND | VDD_EN/VDDQ_EN resistance to GND | 500 | kΩ | |||
| THERMAL PROTECTION | ||||||
| TOTP | OTP trip threshold | 150 | °C | |||
| TOTPHSY | OTP hysteresis | 20 | °C | |||