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ZHCSK81A September 2019 – October 2020 TPS65296

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RJE|18
- MPQF488C

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcsk81a_oa

6.5 Electrical Characteristics

T_J=-40^oC to 125^oC, V_PVIN=12V, V_{PVIN_VDD1}=5V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY VOLTAGE
I_{VCC_5V}	VCC_5V supply current	V_{VDD_EN} = V_{VDDQ_EN} = 0 V		5		μA
		V_{VDD_EN} = 5 V, V_{VDDQ_EN} = 0 V, no load		110		μA
		V_{VDD_EN} = V_{VDDQ_EN} = 5 V, no load		150		μA
VIN	PVIN input voltage range		4.5		18	V
UVLO
UVLO	VCC_5V under-voltage lockout	Wake up VCC_5V voltage		4.1	4.5	V
		Shut down VCC_5V voltage	3.3	3.6		V
		Hysteresis VCC_5V voltage		500		mV
VDD2
V_VDD2SNS	VDD2 sense voltage		1.1	1.115	1.13	V
I_VDD2SNS	VDD2SNS input current	V_VDD2SNS =1.1 V		40		μA
I_VDD2DIS	VDD2 discharge current	V_{VDD_EN} = V_{VDDQ_EN} = 0 V, V_VDD2SNS = 0.5 V		12		mA
t_VDD2SS	VDD2 soft-start time			1.6	2.65	ms
t_VDD2DLY	VDD2 ramp up delay time		1.3	2	3.5	ms
R_DSONH	High-side switch resistance	T_J = 25°C, V_{VCC_5V} = 5V		22		mΩ
R_DSONL	Low-side switch resistance	T_J = 25°C, V_{VCC_5V} = 5V		8.6		mΩ
I_VDD2OCL	Low-side valley current limited	V_OUT = 1.1 V, L = 0.68 μH	8.2	9.8	11.5	A
f_sw	VDD2 switching freqency			600		kHz
t_OFF(MIN)	Minimum off time			198		ns
PGOOD (VDD2, VDD1)
V_THPG	PGOOD threshold	VDD2SNS / VDD1SNS falling (Fault)		87		%
		VDD2SNS / VDD1SNS rising (Good)		93		%
		VDD2SNS / VDD1SNS rising (Fault)		115		%
		VDD2SNS / VDD1SNS falling (Good)		110		%
I_PGMAX	PG sink current	V_PGOOD =0.5V, V_{VDD_EN} =V_{VDDQ_EN} = 5 V, no load		46		mA
t_PGDLY	PG start-up delay	PG from low to high		1		ms
VDD1
V_VDD1SNS	VDD1 sense voltage		1.75	1.8	1.85	V
I_VDD1SNS	VDD1SNS input current	V_VDD1SNS =1.8 V		20		μA
I_VDD1DIS	VDD1 discharge current	V_{VDD_EN} = V_{VDDQ_EN} = 0 V, V_VDD1SNS = 0.5 V		12		mA
t_VDD1SS	VDD1 soft-start time			1.0	2	ms
R_DSONH	High-side switch resistance	T_J = 25°C, V_{PVIN_VDD1} = 5V, V_{VCC_5V} = 5V		150		mΩ
R_DSONL	Low-side switch resistance	T_J = 25°C, V_{PVIN_VDD1}=5V, V_{VCC_5V} = 5V		120		mΩ
I_VDD1OCL	Low-side valley current limited	V_VDD1SNS = 1.8 V, L = 4.7 μH	1.05	1.6	2.1	A
f_sw	VDD1 switching frequency			580		kHz
t_OFF(MIN)	Minimum off time			195		ns
t_OOA	OOA mode operation period	V_VDD1SNS =1.8 V		31		μs
OVP AND UVP (VDD2, VDD1)
V_OVP	OVP threshold voltage	OVP detect voltage	120	125	130	%
V_UVP1	UVP threshold voltage	UVP detect voltage	57.5	62.5	67.5	%
t_OVPDLY	OVP delay			20		μs
t_UVPDLY	UVP delay			250		μs
VDDQ OUTPUT
V_VDDQ	Output voltage	T_J = 25°C, I_VDDQ ≤1.5A	0.57	0.6	0.63	V
I_VDDQOCLSRC	Source current limit	V_VDD2SNS = 1.1 V, V_VDDQ= V_VDDQSNS= 0.5 V	1.7	2.2		A
I_VDDQLK	Leakage current	T_J = 25°C, V_{VDD_EN} = 5 V, V_{VDDQ_EN} = 5 V			5	μA
I_VDDQSNSBIAS	VDDQSNS input bias current	V_{VDD_EN} = 5 V, V_{VDDQ_EN} = 5 V	–0.5	0	0.5
I_VDDQSNSLK	VDDQSNS leakage current	V_{VDD_EN} = 5 V, V_{VDDQ_EN} = 0 V	–1	0	1
I_VDDQDLY	VDDQ output delay relative to VDDQ_EN				35	us
I_VDDQDIS	VDDQ discharge current	T_J = 25°C, V_{VDD_EN} = V_{VDDQ_EN} = 0 V, V_VDD2SNS = 1.1 V, V_VDDQ =0.5V		5.7		mA
VDD_EN, VDDQ_EN LOGIC THRESHOLD
V_IH	VDD_EN/VDDQ_EN high-level voltage		1.35			V
V_IL	VDD_EN/VDDQ_EN low-level voltage				0.5	V
R_TOGND	VDD_EN/VDDQ_EN resistance to GND			500		kΩ
THERMAL PROTECTION
T_OTP	OTP trip threshold			150		°C
T_OTPHSY	OTP hysteresis			20		°C