主頁 接口 LVDS、M-LVDS 和 PECL IC

SN65LVDS348

正在供貨

具有 –4V 至 5V 共模范圍的四路 LVDS 接收器

產(chǎn)品詳情

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 560 Input signal CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 560 Input signal CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm2 9.9 x 6 TSSOP (PW) 16 32 mm2 5 x 6.4
  • Meets or Exceeds the Requirements of ANSI TIA/EIA-644A Standard
  • Single-Channel Signaling Rates1 up to 560 Mbps
  • –4 V to 5 V Common-Mode Input Voltage Range
  • Flow-Through Architecture
  • Active Failsafe Assures a High-level Output When an Input Signal Is not Present
  • SN65LVDS348 Provides a Wide Common-Mode Range Replacement for the SN65LVDS048A or the DS90LV048A
  • APPLICATIONS
    • Logic Level Translator
    • Point-to-Point Baseband Data Transmission Over 100- Media
    • ECL/PECL-to-LVTTL Conversion
    • Wireless Base Stations
    • Central Office or PABX Switches

1The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
  • Meets or Exceeds the Requirements of ANSI TIA/EIA-644A Standard
  • Single-Channel Signaling Rates1 up to 560 Mbps
  • –4 V to 5 V Common-Mode Input Voltage Range
  • Flow-Through Architecture
  • Active Failsafe Assures a High-level Output When an Input Signal Is not Present
  • SN65LVDS348 Provides a Wide Common-Mode Range Replacement for the SN65LVDS048A or the DS90LV048A
  • APPLICATIONS
    • Logic Level Translator
    • Point-to-Point Baseband Data Transmission Over 100- Media
    • ECL/PECL-to-LVTTL Conversion
    • Wireless Base Stations
    • Central Office or PABX Switches

1The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

The SN65LVDS348, SN65LVDT348, SN65LVDS352, and SN65LVDT352 are high-speed, quadruple differential receivers with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3-V of ground noise or a variety of differential and single-ended logic levels. The ’348 is in a 16-pin package to match the industry-standard footprint of the DS90LV048. The ’352 adds two additional VCC and GND pins in a 24-pin package to provide higher data transfer rates with multiple receivers in operation. All offer a flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers. LVDT versions of both integrate a 110- line termination resistor.

These receivers also provide 3x the standard’s minimum common-mode noise voltage tolerance. The –4 V to 5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for more details on the ECL/PECL to LVDS interface.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent-pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling.

The SN65LVDT348 and SN65LVDT352 include an integrated termination resistor. This reduces board space requirements and parts count by eliminating the need for a separate termination resistor. This can also improve signal integrity at the receiver by reducing the stub length from the line termination to the receiver.

The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS348, SN65LVDT348, SN65LVDS352 and SN65LVDT352 are characterized for operation from –40°C to 85°C.

The SN65LVDS348, SN65LVDT348, SN65LVDS352, and SN65LVDT352 are high-speed, quadruple differential receivers with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3-V of ground noise or a variety of differential and single-ended logic levels. The ’348 is in a 16-pin package to match the industry-standard footprint of the DS90LV048. The ’352 adds two additional VCC and GND pins in a 24-pin package to provide higher data transfer rates with multiple receivers in operation. All offer a flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers. LVDT versions of both integrate a 110- line termination resistor.

These receivers also provide 3x the standard’s minimum common-mode noise voltage tolerance. The –4 V to 5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for more details on the ECL/PECL to LVDS interface.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent-pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling.

The SN65LVDT348 and SN65LVDT352 include an integrated termination resistor. This reduces board space requirements and parts count by eliminating the need for a separate termination resistor. This can also improve signal integrity at the receiver by reducing the stub length from the line termination to the receiver.

The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS348, SN65LVDT348, SN65LVDS352 and SN65LVDT352 are characterized for operation from –40°C to 85°C.
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頂層文檔 類型 標(biāo)題 格式選項(xiàng) 下載最新的英語版本 日期
* 數(shù)據(jù)表 Quad High-Speed Differential Receivers 數(shù)據(jù)表 (Rev. E) 2004年 5月 5日
應(yīng)用簡報 LVDS to Improve EMC in Motor Drives 2018年 9月 27日
應(yīng)用簡報 How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018年 8月 3日
應(yīng)用簡報 How to Terminate LVDS Connections with DC and AC Coupling 2018年 5月 16日
應(yīng)用手冊 SN65LVDS348 vs SN65LVDS349 2010年 10月 5日
應(yīng)用手冊 An Overview of LVDS Technology 1998年 10月 5日

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SN65LVDS348 IBIS Model

SLLC080.ZIP (4 KB) - IBIS Model
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